Tài liệu COMPUTER SYSTEMS ORGANIZATION-2 ppt

2
COMPUTER SYSTEMS
ORGANIZATION

1


Central processing unit (CPU)

Control
unit
Arithmetic
logical unit
(ALU)

I/O devices

Registers

…

…

Main
memory

Disk

Printer

Bus

Figure 2-1. The organization of a simple computer with one
CPU and two I/O devices.


A+B

A

Registers

B

A

B

ALU input register
ALU input bus

ALU

A+B

ALU output register

Figure 2-2. The data path of a typical von Neumann machine.


public class Interp {

static int PC;
static int AC;
static int instr;
static int instr3type;
static int data3loc;
static int data;
static boolean run3bit = true;

// program counter holds address of next instr
// the accumulator, a register for doing arithmetic
// a holding register for the current instruction
// the instruction type (opcode)
// the address of the data, or −1 if none
// holds the current operand
// a bit that can be turned off to halt the machine

public static void interpret(int memory[ ], int starting3address) {
// This procedure interprets programs for a simple machine with instructions having
// one memory operand. The machine has a register AC (accumulator), used for
// arithmetic. The ADD instruction adds am integer in memory to the AC, for example
// The interpreter keeps running until the run bit is turned off by the HALT instruction.
// The state of a process running on this machine consists of the memory, the
// program counter, the run bit, and the AC. The input parameters consist of
// of the memory image and the starting address.
PC = starting 3address;
while (run3bit) {
instr = memory[PC];
// fetch next instruction into instr
PC = PC + 1;
// increment program counter

instr3type = get3instr3type(instr);
// determine instruction type
data3loc = find3data(instr, instr3type);
// locate data (−1 if none)
if (data3loc >= 0)
// if data3loc is −1, there is no operand
data = memory[data 3loc]; // fetch the data
execute(instr 3type, data);
//execute instruction
}
}
private static int get3instr3type(int addr) { ... }
private static int find3data(int instr, int type) { ... }
private static void execute(int type, int data){ ... }
}

Figure 2-3. An interpreter for a simple computer (written in Java).


S1

S2

S3

S4

S5

Instruction

fetch
unit

Instruction
decode
unit

Operand
fetch
unit

Instruction
execution
unit

Write
back
unit

(a)
S1:

1

S2:

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

1

2

3

4

5

6

1

2

3

4

5

6

7

8

9

S3:
S4:
S5:
1

2

3

4
5
Time
(b)

…

Figure 2-4. (a) A five-stage pipeline. (b) The state of each
stage as a function of time. Nine clock cycles are illustrated.

S1

Instruction
fetch
unit

S2

S3

S4

S5

Instruction
decode
unit

Operand
fetch
unit

Instruction
execution
unit

Write
back

unit

Instruction
decode
unit

Operand
fetch
unit

Instruction
execution
unit

Write
back
unit

Figure 2-5. (a) Dual five-stage pipelines with a common instruction fetch unit.


S4
ALU

ALU
S1

S2

S3

Instruction
fetch
unit

Instruction
decode
unit

Operand
fetch
unit

S5
LOAD

Write
back
unit

STORE

Floating
point

Figure 2-6. A superscalar processor with five functional units.


Control unit
Broadcasts instructions

8 × 8 Processor/memory grid
Processor
Memory

Figure 2-7. An array processor of the ILLIAC IV type.


Local memories

Shared
memory
CPU

CPU

CPU

CPU

Shared
memory
CPU

CPU

CPU

CPU

Bus
(a)

Bus
(b)

Figure 2-8. (a) A single-bus multiprocessor. (b) A multicomputer with local memories.


Address

Address

1 Cell

Address

0

0

0

1

1

1

2

2

2

3

3

3

4

4

4

5

5

5

6

6

16 bits

7

7

(c)

8

12 bits

9

(b)

10
11
8 bits
(a)

Figure 2-9. Three ways of organizing a 96-bit memory.


2222222222222222222222222222222222
12222222222222222222222222222222222
1 Bits/cell 1
Computer
1
1
1
Burroughs B1700
1

21 222222222222222222222222222222222
1
1
12222222222222222222222222222222222
1
1
IBM PC
8
1 DEC PDP-8
1
1
12
21 222222222222222222222222222222222
1
1
IBM 1130
16
12222222222222222222222222222222222
1
1
1 DEC PDP-15
1
1
18
21 222222222222222222222222222222222
1
1
XDS 940
24
12222222222222222222222222222222222

1
1
12222222222222222222222222222222222
1
1
Electrologica X8
27
1
1
1
XDS Sigma 9
32
21 222222222222222222222222222222222
1
1
12222222222222222222222222222222222
1
1
Honeywell 6180
36
1 CDC 3600
1
1
48
21 222222222222222222222222222222222
1
1
CDC Cyber
60
12222222222222222222222222222222222

1
1
Figure 2-10. Number of bits per cell for some historically interesting commercial computers.


Address

Little endian

Big endian

Address

0

0

1

2

3

3

2

1

0

0

4

4

5

6

7

7

6

5

4

4

8

8

9

10

11

11

10

9

8

8

12

12

13

14

15

15

14

13

12

12

Byte

Byte
32-bit word

32-bit word

(a)

(b)

Figure 2-11. (a) Big endian memory. (b) Little endian memory.


Big endian

Transfer from
big endian to
little endian

Little endian

0

J

I

M

4

S

M

I

T

8

H

0

0

12

0

16

0

M

I

J

J

I

M

T

I

M

S

S

M

I

T

4

0

0

0

H

H

0

0

0

8

12

21 0

0

0

0

0

0 21 12

16

4

0

0

0

0

1

M

I

J

0

T

I

M

S

4

0

0

0

0

H

8

0

0 21

0

0

0 21

0

1

0

0

1

(a)

4

(b)

4

Transfer and
swap

1
(c)

(d)

Figure 2-12. (a) A personnel record for a big endian machine.
(b) The same record for a little endian machine. (c) The result
of transferring the record from a big endian to a little endian.
(d) The result of byte-swapping (c).

0

4 16

22222222222222222222222222222222222222222222222222222
122222222222222222222222222222222222222222222222222222
Word size 1 Check bits 1 Total size 1 Percent overhead 1
1
1
1
1
1
8
4
12
50
22222222222222222222222222222222222222222222222222222
1
1
1
1
1
122222222222222222222222222222222222222222222222222222
1
1
1
1
16
5
21
31
1
1

1
1
1
32
6
38
19
22222222222222222222222222222222222222222222222222222
1
1
1
1
1
64
7
71
11
122222222222222222222222222222222222222222222222222222
1
1
1
1
1
1
1
1
1
128
8
136

6
22222222222222222222222222222222222222222222222222222
1
1
1
1
1
256
9
265
4
122222222222222222222222222222222222222222222222222222
1
1
1
1
122222222222222222222222222222222222222222222222222222
11
11
11
11
512
10
522
2
1
Figure 2-13. Number of check bits for a code that can correct
a single error.

A
0
1

1

C

A

A

0

0

1

0
1

1

0

1
1

1

C

0
Parity
bits

B
(a)

1

0
0

B

C

Error

(b)

0
B
(c)

Figure 2-14. (a) Encoding of 1100. (b) Even parity added. (c) Error in AC.


Memory word 1111000010101110

0
1

0
2

1
3

0
4

1
5

1
6

1
7

0
8

0 0 0 0 1 0 1 1 0 1 1 1 0
9 10 11 12 13 14 15 16 17 18 19 20 21

Parity bits

Figure 2-15. Construction of the Hamming code for the

memory word 1111000010101110 by adding 5 check bits to the
16 data bits.


Main
memory
CPU
Cache

Bus
Figure 2-16. The cache is logically between the CPU and
main memory. Physically, there are several possible places it
could be located.


4-MB
memory
chip
Connector
Figure 2-17. A single inline memory module (SIMM) holding
32 MB. Two of the chips control the SIMM.


Registers
Cache

Main memory

Magnetic disk

Tape

Optical disk

Figure 2-18. A five-level memory hierarchy.


Intersector gap
or
ect
1s

ta bits
6 da
409

ble
am
e
Pr

Track
width is
5–10 microns

E
C
C

Direction

of arm
motion

Width of
1 bit is
0.1 to 0.2 microns

Dire
c
Preamb
le

Read/write
head

tion

of
d

isk

40
96
da
ta

rot
ati
on

bit
s
C

C

E

Disk
arm

Figure 2-19. A portion of a disk track. Two sectors are illustrated.