tong hop cac bai tap vhdl

BAI 1:
1>DFF dong bo rst.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
en$ty DFF_DONGBO is
port(
CLK : in STD_LOGIC;
D : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC
);
end DFF_DONGBO;
architecture DFF_DONGBO of DFF_DONGBO is
begin
process(d,clk,rst)
begin
if (rst='1')and (clk'event and clk='1') then
q<='0' ;
elsif clk'event and clk='1' then
q<=d;
end if;
end process;
end DFF_DONGBO;
2> DFF khong dong bo rst.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
en$ty DFF_KHONGDONGBO is
port(
D : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC;

Q : out STD_LOGIC
);
end DFF_KHONGDONGBO;
architecture DFF_KHONGDONGBO of DFF_KHONGDONGBO is
begin
process(d,clk,rst)
begin
if rst='1' then
q<='0';
elsif clk'event and clk='1' then
q<=d;
end if;
end process;
end DFF_KHONGDONGBO;
3> RSFF khong dong bo.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
en$ty RSFF is
port(
R : in STD_LOGIC;
S : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC
);
end RSFF;
architecture RSFF of RSFF is
signal y: std_logic_vector(1 downto 0);
begin
process(r,s,clk,rst)

variable A: std_logic:='0';
begin
y <=r&s;
if rst='1' then
q<='0';
elsif clk'event and clk='1' then
if y="00" then
q<=a;
elsif y="10" then
q<='0' ;
elsif y="01" then
q<='1' ;
elsif y="11" then
q<='X';
end if;
end if;
end process;
end RSFF;
4> RSFF dong bo.
architecture RSFF_DONGBO of RSFF_DONGBO is
signal y: std_logic_vector(1 downto 0);
begin
process(r,s,clk,rst)
variable A: std_logic:='0';
begin
y <=r&s;
if (rst='1') AND (clk'event and clk='1') then
q<='0';
elsif clk'event and clk='1' then
if y="00" then

q<=a;
elsif y="10" then
q<='0' ;
elsif y="01" then
q<='1' ;
elsif y="11" then
q<='X' ;
end if;
end if;
end process;
end RSFF_DONGBO;
BAI2:
1> Mach demux 8_1;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
en$ty DEMUX8_1 is
port(
d : in STD_LOGIC;
c: in STD_LOGIC_VECTOR(2 downto 0);
Q : out STD_LOGIC_VECTOR(7 downto 0)
);
end DEMUX8_1;
architecture DEMUX8_1 of DEMUX8_1 is
begin
process(d,c)
begin
Q(0)<= D and (not(C(2)) and (not(C(1)) and not(C(0))));
Q(1)<= D and (not(C(2)) and (not(C(1)) and (C(0))));
Q(2)<= D and (not(C(2)) and ((C(1)) and not(C(0))));
Q(3)<= D and (not(C(2)) and ((C(1)) and (C(0))));

Q(4)<= D and ((C(2)) and (not(C(1)) and not(C(0))));
Q(5)<= D and ((C(2)) and (not(C(1)) and (C(0))));
Q(6)<= D and ((C(2)) and ((C(1)) and not(C(0))));
Q(7)<= D and ((C(2)) and ((C(1)) and (C(0))));
end process;
end DEMUX8_1;
2> Thiet ke mach giai gray.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
en$ty gm_7seg is
port(
en : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(2 downto 0);
b : out STD_LOGIC_VECTOR(2 downto 0)
);
end gm_7seg;
architecture gm_7seg of gm_7seg is
begin
process(a,en)
begin
case A is
when "000"=>b<="000";
when"001"=>b<="001";
when"010"=>b<="011";
when"011"=>b<="010";
when "100"=>b<="100";
when"101"=>b<="101";
when"110"=>b<="111";
when"111"=>b<="110";
when others=>b<="XXX";

end case;
end process;end gm_7seg;
3>so sanh 2 so nhi phan 4 bit.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
en$ty sscach2 is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
y : out STD_LOGIC_VECTOR(3 downto 0)
);
end sscach2;
architecture sscach2 of sscach2 is
func$on chuyen (x:in std_logic_vector(3 downto 0))return integer is
variable r:integer;
begin
r:=conv_integer(x(3))*8+
conv_integer(x(2))*4+conv_integer(x(1))*2+conv_integer(x(0));
return r;
end chuyen;
begin
process(a,b)
begin
if chuyen (a)>chuyen(b)then
y<=a;
else
y<=b;
end if;
end process;

end sscach2;
4. mach giai ma 7 doan.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
en$ty machgiaima7doan is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
y : out STD_LOGIC_VECTOR(7 downto 0)
);
end machgiaima7doan;
architecture machgiaima7doan of machgiaima7doan is
begin
process(a)
begin
case a is
when "0000"=>y<="01000000";
when "0001"=>y<="01111001";
when "0010"=>y<="00100100";
when "0011"=>y<="00110000";
when "0100"=>y<="00011001";
when "0101"=>y<="00010010";
when "0110"=>y<="00000010";
when "0111"=>y<="01111000";
when "1000"=>y<="00000000";
when "1001"=>y<="00010000";
when others =>y<="XXXXXXXX" ;
end case;
end process;
end machgiaima7doan;
5. bo ALU 4 bit;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
en$ty ALU is
port(
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
D : in STD_LOGIC_VECTOR(1 downto 0);
Q : out STD_LOGIC_VECTOR(4 downto 0)
);
end ALU;
architecture ALU of ALU is
func$on chuyen(x:in std_logic_vector(3 downto 0)) return integer is
variable n: integer;
begin
n:=conv_integer(x(3))*8+conv_integer(x(2))*4+conv_integer(x(1))*2+conv_integer(x(0));
return n;
end chuyen;
begin
Process(D,A,B)
begin
if D="00" then cong
Q<=conv_std_logic_vector(chuyen(A)+chuyen(B),5);
elsif D="01" then
Q<=conv_std_logic_vector(chuyen(A)-chuyen(B),5);
elsif D="10" then
Q<=conv_std_logic_vector(chuyen(A)*chuyen(B),5);
else
if B="0000" then
Q<="XXXXX";

else
Q<=conv_std_logic_vector(chuyen(A)/chuyen(B),5);
end if;
end if;
End Process;
end ALU;
BAI3:
1. DEM TIEN LUI KD=16;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
en$ty demkd_16_dungconv is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
s : in STD_LOGIC;
y : out STD_LOGIC_VECTOR(3 downto 0)
);
end demkd_16_dungconv;
architecture demkd_16_dungconv of demkd_16_dungconv is
begin
process(s,clk,rst)
variable x:integer range 0 to 15:=0;
begin
if rst='1' then
x:=0;
elsif clk'event and clk='1' then
if s='1' then
if x=15 then
x:=0;

else
x:=x+1;
end if;
else
if x=0 then
x:=15;
else
x:=x-1;
end if;
end if;
end if;
y<=conv_std_logic_vector(x,4);
end process;
end demkd_16_dungconv;
2.majohson 8 bit.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_arith.all;
en$ty demkd_16_dungconv is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
s : in STD_LOGIC;
y : out STD_LOGIC_VECTOR(3 downto 0)
);
end demkd_16_dungconv;
architecture demkd_16_dungconv of demkd_16_dungconv is
begin
process(s,clk,rst)
variable x:integer range 0 to 15:=0;

begin
if rst='1' then
x:=0;
elsif clk'event and clk='1' then
if s='1' then
if x=15 then
x:=0;
else
x:=x+1;
end if;
else
if x=0 then
x:=15;
else
x:=x-1;
end if;
end if;
end if;
y<=conv_std_logic_vector(x,4);
end process;
end demkd_16_dungconv;
3.ghi dich vao nt ra ss
library IEEE;
use IEEE.STD_LOGIC_1164.all;
en$ty ghidichvaont_ss is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
d : in STD_LOGIC;
y : out STD_LOGIC_VECTOR(7 downto 0)

);
end ghidichvaont_ss;
architecture ghidichvaont_ss of ghidichvaont_ss is
begin
process (clk,rst,d)
variable mang:std_logic_vector(7 downto 0);
variable i:integer:=0;
begin
if rst='1' then
i:=0;
elsif clk'event and clk='1' then
mang(i):=d;
if i=7 then
y<= mang;
else
i:=i+1;
end if;
end if;
end process;
end ghidichvaont_ss;
BAI4:
1.bo dem ma gray.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
en$ty gray4bit is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 downto 0)
);

end gray4bit;
architecture gray4bit of gray4bit is
begin
process(rst,clk)
variable a : integer range 0 to 15 ;
begin
if rst='1' then
Q<="0000";
elsif clk'event and clk='1' then
if a=15 then
a:=0;
else
a:=a+1;
end if;
end if;
case a is
when 0=>Q<="0000" ;
when 1=>Q<="0001";
when 2=>Q<="0011";
when 3=>Q<="0010";
when 4=>Q<="0110";
when 5=>Q<="0111";
when 6=>Q<="0101";
when 7=>Q<="0100";
when 8=>Q<="1100";
when 9=>Q<="1101";
when 10=> Q<="1111";
when 11=>Q<="1110";
when 12=>Q<="1010";
when 13=>Q<="1011";

when 14=>Q<="1001";
when 15=>Q<="1000";
when others => Q<= "XXXX";
end case;
end process;
end gray4bit;
2.ma vong 4bit
library IEEE;
use IEEE.STD_LOGIC_1164.all;
en$ty mavong4bit is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC_VECTOR(3 downto 0)
);
end mavong4bit;
architecture mavong4bit of mavong4bit is
type state is(s0,s1,s2,s3);
signal s:state;
begin
next_state :process(rst,clk)
begin
if rst='1' then
s<=s0;
elsif clk'event and clk='1' then
case s is
when s0=>s<=s1;
when s1=>s<= s2;
when s2=>s<=s3;
when s3=>s<=s0;

end case;
end if;
end process;
output: process(s)
begin
case s is
when s0=>y<="0001";
when s1=>y<="0010";
when s2=>y<="0100";
when s3=>y<="1000";
when others =>y<="XXXX";
end case;
end process;
end mavong4bit;
3.thiet ke den gia thong.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_arith.all;
en$ty dengthong is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
v : out STD_LOGIC;
x : out STD_LOGIC;
d : out STD_LOGIC;
ht : out STD_LOGIC_VECTOR(7 downto 0)
);
end dengthong;
architecture dengthong of dengthong is
signal z: std_logic_vector(4 downto 0);

begin
process(clk,rst)
variable a:integer range 0 to 17;
begin
if rst='1' then
a:=0;
elsif clk'event and clk='1' then
if a=17 then
a:=0;
else
a:=a+1;
end if;
if a>0 and a<9 then
v<='0' ;
d<='1';
x<='0';
elsif a>8 and a<15 then
v<='0' ;
d<='0';
x<='1';
elsif a>14 and a<18 then
v<='1' ;
d<='0';
x<='0';
end if;
end if;
case a is
when 0=>ht<="01000000";
when 1=>ht<="01111001";
when 2=>ht<="01000100";

when 3=>ht<="00110000";
when 4=>ht<="00011001";
when 5=>ht<="00010010";
when 6=>ht<="00000001";
when 7=>ht<="01111000";
when 8=>ht<="00000000";

when 9=>ht<="01000000";
when 10=>ht<="01111001";
when 11=>ht<="01000100";
when 12=>ht<="00110000";
when 13=>ht<="00011001";
when 14=>ht<= "00010010";

when 15=>ht<="01000000";
when 16=>ht<="01111001";
when 17=>ht<="01000100";
when others =>ht<="XXXXXXXX";
end case;
z<=conv_std_logic_vector(a,5) ;
end process;
end dengthong;
4.kta dau vao la 1000 thi ra =1;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
en$ty ktr_sdmang is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
d :in std_logic;

y : out STD_LOGIC
);
end ktr_sdmang;
architecture ktr_sdmang of ktr_sdmang is
begin
process(clk,rst)
variable mang:std_logic_vector(3 downto 0) ;
begin
if rst='1' then
y<='0';
elsif clk'event and clk='1' then
mang(3):=mang(2);
mang(2):=mang(1);
mang(1):=mang(0);
mang(0):=d;
if mang="1000" then
y<='1';
else
y<='0';
end if;
end if;
end process;
end ktr_sdmang;