Tài liệu Semiconductor Memories doc

© Digital Integrated Circuits
2nd
Memories
Digital Integrated
Digital Integrated
Circuits
Circuits
A Design Perspective
A Design Perspective
Semiconductor
Semiconductor
Memories
Memories
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
December 20, 2002
© Digital Integrated Circuits
2nd
Memories
Chapter Overview
Chapter Overview

Memory Classification

Memory Architectures

The Memory Core

Periphery


Reliability

Case Studies
© Digital Integrated Circuits
2nd
Memories
Semiconductor Memory Classification
Semiconductor Memory Classification
Read-Write Memory
Non-Volatile
Read-Write
Memory
Read-Only Memory
EPROM
E
2
PROM
FLASH
Random
Access
Non-Random
Access
SRAM
DRAM
Mask-Programmed
Programmable (PROM)
FIFO
Shift Register
CAM
LIFO

© Digital Integrated Circuits
2nd
Memories
Memory Timing: Definitions
Memory Timing: Definitions

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
DATA
WRITE
READ
© Digital Integrated Circuits
2nd
Memories
Memory Architecture: Decoders
Memory Architecture: Decoders



N


N





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S

S

S

S
N


A

A

A
K


K

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
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S
N


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

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N


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

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S

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M
Intuitive architecture for N x M memory
Too many select signals:
N words == N select signals
K = log
2
N
Decoder reduces the number of select signals

M
© Digital Integrated Circuits
2nd
Memories

!

L  K


A
K
A
K  
A
L  
A

M.
K
A
K  
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Array-Structured Memory Architecture
Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word
© Digital Integrated Circuits
2nd
Memories
Hierarchical Memory Architecture
Hierarchical Memory Architecture
Advantages:
Advantages:

1. Shorter wires within blocks
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
2. Block address activates only 1 block => power savings
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$
© Digital Integrated Circuits
2nd
Memories
Block Diagram of 4 Mbit SRAM
Block Diagram of 4 Mbit SRAM
Clock
generator
CS, WE
buffer
I/O
buffer

Y
-address
buffer
X
-address
buffer
x1/x4
controller
Z
-address
buffer
X
-address
buffer
Predecoder and block selector
Bit line load
Transfer gate
Column decoder
Sense amplifier and write driver
[Hirose90]
© Digital Integrated Circuits
2nd
Memories
Contents-Addressable Memory
Contents-Addressable Memory
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© Digital Integrated Circuits
2nd
Memories
Memory Timing: Approaches
Memory Timing: Approaches
DRAM Timing
Multiplexed Adressing
SRAM Timing
Self-timed
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
RAS
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CAS
© Digital Integrated Circuits
2nd
Memories
Read-Only Memory Cells
Read-Only Memory Cells
WL
BL
WL
BL
1
WL
BL
WL
BL
WL
BL
0
V
DD
WL
BL
GND
Diode ROM MOS ROM 1 MOS ROM 2
© Digital Integrated Circuits
2nd
Memories
MOS OR ROM
MOS OR ROM

WL[0]
V
DD
BL[0]
WL[1]
WL[2]
WL[3]
V
bias
BL[1]
Pull-down loads
BL[2] BL[3]
V
DD
© Digital Integrated Circuits
2nd
Memories
MOS NOR ROM
MOS NOR ROM
WL[0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
V
DD
BL [1]
Pull-up devices
BL [2] BL [3]

GND
© Digital Integrated Circuits
2nd
Memories
MOS NOR ROM Layout
MOS NOR ROM Layout
Programmming using the
Active Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (9.5λ x 7λ)
© Digital Integrated Circuits
2nd
Memories
MOS NOR ROM Layout
MOS NOR ROM Layout
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (11λ x 7λ)
Programmming using
the Contact Layer Only
© Digital Integrated Circuits
2nd
Memories
MOS NAND ROM
MOS NAND ROM

All word lines high by default with exception of selected row
WL[0]
WL[1]
WL[2]
WL[3]
V
DD
Pull-up devices
BL[3]BL[2]BL[1]BL[0]
© Digital Integrated Circuits
2nd
Memories
MOS NAND ROM Layout
MOS NAND ROM Layout
No contact to VDD or GND necessary;
Loss in performance compared to NOR ROM
drastically reduced cell size
Polysilicon
Diffusion
Metal1 on Diffusion
Cell (8λ x 7λ)
Programmming using
the Metal-1 Layer Only
© Digital Integrated Circuits
2nd
Memories
NAND ROM Layout
NAND ROM Layout
Cell (5λ x 6λ)
Polysilicon

Threshold-altering
implant
Metal1 on Diffusion
Programmming using
Implants Only
© Digital Integrated Circuits
2nd
Memories
Equivalent Transient Model for MOS NOR ROM
Equivalent Transient Model for MOS NOR ROM

Word line parasitics

Wire capacitance and gate capacitance

Wire resistance (polysilicon)

Bit line parasitics

Resistance not dominant (metal)

Drain and Gate-Drain capacitance
Model for NOR ROM
V
DD
C
bit
r
word
c

word
WL
BL
© Digital Integrated Circuits
2nd
Memories
Equivalent Transient Model for MOS NAND ROM
Equivalent Transient Model for MOS NAND ROM

Word line parasitics

Similar to NOR ROM

Bit line parasitics

Resistance of cascaded transistors dominates

Drain/Source and complete gate capacitance
Model for NAND ROM
V
DD
C
L
r
word
c
word
c
bit
r

bit
WL
BL
© Digital Integrated Circuits
2nd
Memories
Decreasing Word Line Delay
Decreasing Word Line Delay
Metal bypass
Polysilicon word lineK cells
Polysilicon word lineWL
Driver
(b) Using a metal bypass
(a) Driving the word line from both sides
Metal word line
WL
(c) Use silicides
© Digital Integrated Circuits
2nd
Memories
Precharged MOS NOR ROM
Precharged MOS NOR ROM
PMOS precharge device can be made as large as necessary,
but clock driver becomes harder to design.
WL [0]
GND
BL [0]
WL [1]
WL [2]
WL [3]

V
DD
BL [1]
Precharge devices
BL [2] BL [3]
GND
pre
3
© Digital Integrated Circuits
2nd
Memories
Non-Volatile Memories
Non-Volatile Memories
The Floating-gate transistor (FAMOS)
The Floating-gate transistor (FAMOS)
Floating gate
Source
Substrate
Gate
Drain
n
+
n
+_
p
t
ox
t
ox
Device cross-section

Schematic symbol
G
S
D
© Digital Integrated Circuits
2nd
Memories
Floating-Gate Transistor Programming
Floating-Gate Transistor Programming
0 V
2
5 V
0 V
DS
Removing programming
voltage leaves charge trapped
5 V
2
2.5 V
5 V
DS
Programming results in
higher V
T
.
20 V
10 V 5 V
20 V
DS
Avalanche injection

© Digital Integrated Circuits
2nd
Memories
A “Programmable-Threshold” Transistor
A “Programmable-Threshold” Transistor
45-state 45-state
V
T
V
WL
V
GS
“6”
“77 ”