VHDL and verilog user manual

Technical Support Line:
1- 800-LATTICE or (408) 428-6414
pDS1131-UM Rev 7.2.1
VHDL and Verilog
Simulation User Manual
Version 7.2
VHDL and Verilog Simulation User Manual 2
Copyright
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prior written consent from Lattice Semiconductor Corporation.
The software described in this manual is copyrighted and all rights are reserved by
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without notice.
The distribution and sale of this product is intended for the use of the original
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The following trademarks are recognized by Lattice Semiconductor Corporation:
Generic Array Logic, ISP, ispANALYZER, ispATE, ispCODE, ispDCD,
ispDOWNLOAD, ispDS+, ispEXPERT, ispGDS, ispGDX, ispHDL, ispJTAG,
ispSmartFlow, ispStarter, ispSTREAM, ispSVF, ispTA, ispTEST, ispTURBO,
ispVECTOR, ispVerilog, ispVHDL, ispVM, Latch-Lock, pDS+, RFT, Total ISP, and
Twin GLB are trademarks of Lattice Semiconductor Corporation.
E
2
CMOS, GAL, ispGAL, ispLSI, pDS, pLSI, Silicon Forest, and UltraMOS are
registered trademarks of Lattice Semiconductor Corporation.

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Lattice Semiconductor Corporation
5555 NE Moore Ct.
Hillsboro, OR 97124
(503) 268-8000
August 1999
VHDL and Verilog Simulation User Manual 3
Limited Warranty
Lattice Semiconductor Corporation warrants the original purchaser that the Lattice
Semiconductor software shall be free from defects in material and workmanship for a
period of ninety days from the date of purchase. If a defect covered by this limited
warranty occurs during this 90-day warranty period, Lattice Semiconductor will repair
or replace the component part at its option free of charge.
This limited warranty does not apply if the defects have been caused by negligence,
accident, unreasonable or unintended use, modification, or any causes not related to
defective materials or workmanship.
To receive service during the 90-day warranty period, contact Lattice Semiconductor
Corporation at:
Phone: 1-800-LATTICE
Fax: (408) 944-8450

E-mail:
If the Lattice Semiconductor support personnel are unable to solve your problem over
the phone, we will provide you with instructions on returning your defective software
to us. The cost of returning the software to the Lattice Semiconductor Service Center
shall be paid by the purchaser.
Limitations on Warranty
Any applicable implied warranties, including warranties of merchantability and fitness
for a particular purpose, are hereby limited to ninety days from the date of purchase
and are subject to the conditions set forth herein. In no event shall Lattice
Semiconductor be liable for consequential or incidental damages resulting from the
breach of any expressed or implied warranties.
Purchaser’s sole remedy for any cause whatsoever, regardless of the form of action,
shall be limited to the price paid to Lattice Semiconductor for the Lattice
Semiconductor software.
The provisions of this limited warranty are valid in the United States only. Some states
do not allow limitations on how long an implied warranty lasts, or exclusion of
consequential or incidental damages, so the above limitation or exclusion may not
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This warranty provides you with specific legal rights. You may have other rights that
vary from state to state.
VHDL and Verilog Simulation User Manual 4
Table of Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
What Is In This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Where to Look for Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Documentation Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Lattice Semiconductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Cadence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Mentor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Viewlogic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Synopsys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
IEEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Model Technology Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Frontline PureSpeed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Part I: VHDL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Chapter 1 Introduction to VHDL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VHDL Directory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
The VHDL Simulation Library Directory Structure on the UNIX Platform. . . . . . . . . . . . . . 17
Examples Directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Library Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
The VHDL Simulation Library Directory Structure on the PC Platform. . . . . . . . . . . . . . . . 20
Examples Directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Library Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VHDL Simulation Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VHDL Functional Simulation Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VHDL Timing Simulation Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VHDL Module Simulation Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VHDL Functional Simulation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Functional Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Functional Simulation Process Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VHDL Timing Simulation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VHDL Timing Simulation Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VHDL Timing Simulation Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VHDL and Verilog Simulation User Manual 5
Chapter 2 VHDL Simulation with Cadence Leapfrog . . . . . . . . . . . . . . . . . . . . . . . 29
Cadence Leapfrog Simulation Library Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Environment Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Files for Schematic Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Files for Schematic to VHDL Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Files for Simulations and Library Compilation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
VHDL Functional Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
VHDL VITAL Timing Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
VHDL Module Simulation Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
VHDL Functional Simulation with Cadence LeapFrog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Functional Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Command-Line Quick Reference List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Schematic to VHDL Design Conversion Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Design Compilation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Functional Simulation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
VHDL Timing Simulation with Cadence LeapFrog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Timing Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Command-Line Quick Reference List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
VHDL Netlist Generation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Design Elaboration Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Device-Specific Notes for Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
GXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
XTEST_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Chapter 3 VHDL Simulation with Mentor Graphics QuickVHDL . . . . . . . . . . . . 41
Mentor Graphics QuickVHDL Simulation Library Environment . . . . . . . . . . . . . . . . . . . . . . . . 42
Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Environment Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Files for Schematic Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Files for Schematic to VHDL Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Files for Simulation and Library Compilation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
VHDL Functional Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

VHDL VITAL Timing Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
VHDL Module Simulation Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
VHDL Functional Simulation with Mentor Graphics QuickVHDL . . . . . . . . . . . . . . . . . . . . . . . 46
Functional Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Command-Line Quick Reference List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Schematic to VHDL Design Conversion Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Work Library Creation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Design Compilation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Functional Simulation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
VHDL Timing Simulation with Mentor Graphics QuickVHDL. . . . . . . . . . . . . . . . . . . . . . . . . . 48
Timing Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Command-Line Quick Reference List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Design Compilation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
VHDL and Verilog Simulation User Manual 6
Timing Simulation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Device-Specific Notes for Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
GXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
XTEST_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Chapter 4 VHDL Simulation with Synopsys VSS . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Synopsys VSS Simulation Library Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Environment Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Files for Simulation and Library Compilation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VHDL Functional Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VHDL VITAL Timing Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
VHDL Module Simulation Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
VHDL Functional Simulation with Synopsys VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Functional Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
VHDL Timing Simulation with Synopsys VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Timing Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Command-Line Quick Reference List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Design Compilation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Timing Simulation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Device-Specific Notes for Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
GXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
XTEST_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Chapter 5 VHDL Simulation with Viewlogic Vantage . . . . . . . . . . . . . . . . . . . . . . . 62
Viewlogic Vantage Simulation Library Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Environment Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
VHDL Functional Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
VHDL Functional Simulation with Viewlogic Vantage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Functional Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Command-Line Quick Reference List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Schematic to VHDL Design Conversion Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Work Library Creation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Design Compilation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Functional Simulation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
VHDL Timing Simulation with Viewlogic Vantage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Timing Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Command-Line Quick Reference List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Work Library Creation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Design Compilation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Functional Simulation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Device-Specific Notes for Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
GXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
XTEST_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
VHDL and Verilog Simulation User Manual 7

Chapter 6 VHDL Simulation with Model Technology V-System/VHDL . . . . . . 71
Model Technology V-System Simulation Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . 72
VHDL Functional Library Compilation Steps: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
VHDL Timing Library Compilation Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
VHDL Module Simulation Library Compilation Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
VHDL Functional Simulation Using Model Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Functional Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
VHDL Timing Simulation using Model Technology V-System . . . . . . . . . . . . . . . . . . . . . . . . . 76
Timing Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Command-Line Quick Reference List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Timing Simulation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Device-Specific Notes for Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
GXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
XTEST_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Chapter 7 VHDL Simulation with Viewlogic Speedwave . . . . . . . . . . . . . . . . . . . 80
Viewlogic Speedwave Simulation Library Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Library Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
VHDL Functional Library Compilation Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
VHDL Timing Library Compilation Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
VHDL Module Simulation Library Compilation Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
VHDL Functional Simulation Using Viewlogic Speedwave . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Functional Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
VHDL Timing Simulation using Viewlogic Speedwave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Timing Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Device-Specific Notes for Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
GXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
XTEST_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Part II: Verilog Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Chapter 8 Introduction to Verilog Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Verilog Directory Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Examples Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Library Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Verilog Simulation Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Verilog Functional Simulation Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Verilog Timing Simulation Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Verilog Module Simulation Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Verilog Functional Simulation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Verilog Timing Simulation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
VHDL and Verilog Simulation User Manual 8
Chapter 9 Verilog Simulation with Cadence Verilog-XL . . . . . . . . . . . . . . . . . . . . 94
Verilog Functional Simulation with Cadence Verilog-XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Functional Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Test Fixture File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Verilog Netlist Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Command-Line Quick Reference List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Functional Simulation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Verilog Timing Simulation with Cadence Verilog-XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Timing Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Command Line Quick-Reference List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Create Simulation Input Files Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Timing Simulation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
System Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Device-Specific Notes for Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
GXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
XTEST_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Chapter 10 Verilog Simulation with Frontline PureSpeed . . . . . . . . . . . . . . . . . 100
Verilog Functional Simulation with Frontline PureSpeed. . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Functional Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Test Fixture File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Verilog Timing Simulation with Frontline PureSpeed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Timing Simulation Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Test Fixture File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Back-Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SDF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Header Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Cell Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
System Task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Device-Specific Notes for Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
GXRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
XTEST_OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Appendix A Bus/Vector Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Bus/Vector Reconstruction Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
EDIF Constructs Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
EDIF Rename Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
EDIF Array Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
EDIF Member Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
User-Controlled Options for EDIF Array Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Specifying Index Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Specifying Least Significant Bit (LSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Array Definition File Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
VHDL and Verilog Simulation User Manual 9
Preface
The LSC HDL Simulation Library Package from Lattice™ Semiconductor Corporation
(LSC, Lattice) contains VHDL and Verilog-compatible libraries for functional and
timing simulation. It also includes the Module Simulation library to support the 6000
family of devices.
This manual describes how to use the VHDL and Verilog Simulation Libraries from
Lattice to perform functional and timing simulation using one of the following

simulators: Cadence LeapFrog™, Mentor QuickVHDL
®
, Viewlogic Vantage
®
,
Synopsys
®
VSS™, Cadence Verilog XL, Frontline PureSpeed™, or any OVI-
compliant Verilog™ simulator. Simulation can be performed on schematic designs
that have been created in Cadence Concept™, Mentor’s Design Architect
®
, and
Viewlogic’s Viewdraw
®
environment and then converted to VHDL or Verilog.
Simulation can also be performed on VHDL or Verilog designs created using Lattice
Semiconductor macros.
The VHDL libraries are designed for use with:
■ Cadence Leapfrog VHDL simulator
■ Mentor QuickVHDL simulator
■ Viewlogic Vantage VHDL simulator
■ Synopsys VSS (VHDL System Simulator)
■ Model Technology V-System/VHDL simulator
■ Any IEEE 1076-87 compliant VHDL simulator
The Verilog libraries are designed for use with:
■ Cadence Verilog-XL
■ Frontline PureSpeed
■ Any OVI-compliant simulator
This manual is intended for use by engineers who are knowledgeable in VHDL and
Verilog system design and architecture. It also assumes that you are familiar with the

ispEXPERT™ software and a VHDL or Verilog simulator. For additional information
on VHDL and Verilog, refer to the appropriate reference material listed under
“Related Documentation.”
What Is In This Manual
VHDL and Verilog Simulation User Manual 10
What Is In This Manual
This user manual contains information on the following topics for each supported
simulator:
■ Environment Setup
■ Prerequisite Files
■ Required Files and Libraries
■ Compiling the Lattice VHDL and Simulation Libraries
■ Design Flows for Functional and Timing Simulation
Where to Look for Information
Part I, VHDL Simulation
Chapter 1, Introduction to VHDL Simulation
– Describes the VHDL functional and
timing simulation flow. It also identifies the directory structure of the files in the VHDL
Simulation Libraries.
Chapter 2, VHDL Simulation with Cadence Leapfrog
– Provides information on the
environment setup, prerequisite files, compiling the simulation libraries, and
simulation steps for the Cadence Leapfrog simulator.
Chapter 3, VHDL Simulation with Mentor Graphics QuickVHDL
– Provides
information on the environment setup, prerequisite files, and compiling the simulation
libraries.
Chapter 4, VHDL Simulation with Synopsys VSS
– Provides information on the
environment setup, prerequisite files, compiling the simulation libraries, and

simulation steps for the Synopsys VSS simulator.
Chapter 5, VHDL Simulation with Viewlogic Vantage
– Provides information on the
environment setup, prerequisite files, compiling the simulation libraries, and
simulation steps for the Viewlogic Vantage simulator.
Chapter 6, VHDL Simulation with Model Technology V-Tech
– Provides
information on the environment setup, prerequisite files, compiling the simulation
libraries, and simulation steps for the Model Technology V-Tech simulator.
Chapter 7, VHDL Simulation with Viewlogic Speedwave
– Provides information on
the environment setup, prerequisite files, compiling the simulation libraries, and
simulation steps for the Viewlogic Speedwave simulator.
Where to Look for Information
VHDL and Verilog Simulation User Manual 11
Part II, Verilog Simulation
Chapter 8, Introduction to Verilog Simulation
– Describes the Verilog functional
and timing simulation flow. It also identifies the directory structure of the files in the
Verilog Simulation Libraries.
Chapter 9, Verilog Simulation with Cadence Verilog-XL
– Provides information on
the environment setup, prerequisite files, compiling the simulation libraries, and
simulation steps for the Cadence Verilog-XL simulator.
Chapter 10, Verilog Simulation with Frontline PureSpeed
– Provides information
on the environment setup, prerequisite files, compiling the simulation libraries, and
simulation steps for the Frontline PureSpeed simulator.
Appendix A, Bus/Vector Reconstruction
– Describes reconstructing buses and

vectors for Verilog and VHDL outputs using an array definition file.
Documentation Conventions
VHDL and Verilog Simulation User Manual 12
Documentation Conventions
The software manuals use the following conventions.
Convention Definition and Usage
Italics
Italicized text represents variable input. For example:
design
.1
This means you must replace
design
with the file name you have
used for all the files relevant to your design.
Valuable information may be italicized for emphasis.
Book titles also appear in italics.
The beginning of a procedure appears in italics. For example:
To open a design
:
Bold Valuable information may be boldfaced for emphasis. Commands
are shown in boldface. Buttons on dialog box are also boldfaced.
For example:
Type edif2laf at the command line.
Courier
Font
Monospaced (Courier) font indicates file and directory names and
text that the system displays. For example:
set path = ($path $LATTICE)
Bold
Courier

Bold Courier font indicates text you type in response to system
prompts. For example:
cp license.tmp license.dat
| | Vertical bars indicate options that are mutually exclusive; you can
select only one. For example:
REGTYPE GLB|IOC
“Quotes” Titles of chapters or sections in chapters in this manual are shown
in quotation marks and bold, blue, underscored type to indicate
jumps to the specified chapter, section, or page. For example:
See
Chapter 1, “Introduction to VHDL Simulation.”
✍
NOTE
Indicates a special note.
▲ CAUTION Indicates a situation that could cause loss of data or other
problems.
❖ TIP Indicates a special hint that makes using the software easier.
⇒ Indicates a menu option leading to a submenu option. For
example:
File ⇒ New
Related Documentation
VHDL and Verilog Simulation User Manual 13
Related Documentation
In addition to this supplement, the following documentation is helpful when using the
Lattice Semiconductor VHDL/Verilog Simulation Library:
Lattice Semiconductor
■
ispEXPERT Compiler User Manual
■
ispEXPERT Compiler and Cadence Design Manual

■
ispEXPERT Compiler and Mentor Graphics Design Manual
■
ispEXPERT Compiler and Synopsys Design Manual
■
ispEXPERT Compiler and Viewlogic Design Manual
■
Macro Library Reference Manual
■
5K/8K Macro Library Supplement
Cadence
■
HDL Desktop Reference Manual
■
LeapFrog VHDL User Guide
■
LeapFrog VHDL Simulator Reference Manual
■
VHDLLink User Guide
Mentor
■
QuickSim II User’s and Reference Manual
■
QuickVHDL User’s and Reference Manual
■
VHDLwrite User’s and Reference Manual
Viewlogic
■
Viewsim/VHDL User Guide
Synopsys

■
VHDL System Simulator Tutorial
■
VHDL System Simulator Command Reference Manual
■
VHDL System Simulator User’s Manual
■
Library Compiler Reference Manual
IEEE
■
IEEE Standard VHDL Language Reference Manual 1076-87, 1076-93
Related Documentation
VHDL and Verilog Simulation User Manual 14
OVI
■
Standard Delay Format Specification
(Version 2.1)
■
Verilog HDL Reference
(version 1.0)
Model Technology Inc.
■
V-System/VHDL Windows User’s Manual
Frontline PureSpeed
■
PureSpeed User’s Manual
Part I: VHDL Simulation
VHDL and Verilog Simulation User Manual 16
Chapter 1
Introduction to VHDL Simulation

The VHDL Simulation library from Lattice Semiconductor Corporation (LSC) contains
VHDL libraries for functional and timing simulation. The VHDL libraries are designed
for use with:
■ Cadence Leapfrog VHDL simulator *
■ Mentor Graphics QuickVHDL simulator *
■ Viewlogic Vantage VHDL simulator
■ Synopsys VSS (VHDL System Simulator) *
■ Model Technology V-System/VHDL simulator *
■ Viewlogic Speedwave simulator*
* These simulators also support the module devices (6000 family) from Lattice
Semiconductor Corporation. Refer to the
ISP Encyclopedia
for details on the module
devices.
The functional simulation library conforms to IEEE 1076-87 standards. The VITAL
timing library conforms to VITAL 3.0 standards.
This chapter describes the VHDL Simulation library directory structure. It also
provides an overview of functional and timing simulation.
VHDL Directory Structure
VHDL and Verilog Simulation User Manual 17
VHDL Directory Structure
The VHDL Simulation library contains source files and examples for functional and
timing (with or without VITAL acceleration) simulation. It also provides other vendor-
dependent option files required to compile and use the libraries.
The VHDL Simulation Library Directory Structure on the UNIX Platform
The simulators supported on the UNIX platform are: Cadence Leapfrog, Mentor
QuickVHDL, Viewlogic Vantage VHDL, and Synopsys VSS (VHDL System
Simulator). Figure 1-1 shows the directory structure for the UNIX platform.
Figure 1-1. VHDL Simulation Library Directory Structure on UNIX Platforms
<

ispcomp_vhdl
>
examples
library
leapfrog
qvhdl
vantage
vss
src vss
func_lib
time_lib
lsc_mod
options
leapfrog
func_lib
time_lib
lsc_mod
options
qvhdl
func_lib
time_lib
options
vantage
options
func_lib
lsc_mod
VHDL Directory Structure
VHDL and Verilog Simulation User Manual 18
Examples Directory
The examples directory contains examples for each design environment:

■ leapfrog – contains files for Cadence Leapfrog
■ qvhdl – contains files for Mentor QuickVHDL
■ vantage – contains files for Viewlogic Vantage
■ vss – contains files for Synopsys VSS
Each of the vendor subdirectories contains the following examples:
■ jkff – a JK flip-flop
■ traffic – a traffic light controller
■ multfifo – a module (FIFO-multiplier)
A step-by-step description is given for both functional and timing simulation using
either the “jkff” schematic design example or the “multfifo” example in Verilog or
VHDL design format.
Library Directory
The library directory contains five subdirectories. Many of the files are libraries that
need to be compiled into directories prior to running simulation. Please refer to the
appropriate simulator chapter for instructions on compiling the libraries for the
simulator you are using.
■ src – contains the following:
• Functional simulation library source file, func_src.vhd
• Timing simulation library source file, vital30.vhd
• Module simulation library source file, lscmod.vhd, for the 6000 family of
devices
■ leapfrog – contains the following:
• func_lib – functional simulation library lat_vhd needs to be compiled into this
directory.
• time_lib – timing simulation library lat_vitl needs to be compiled into this
directory.
• lsc_mod – module simulation library lsc_mod needs to be compiled into this
directory.
• options – options files required for functional and timing simulation.
VHDL Directory Structure

VHDL and Verilog Simulation User Manual 19
■ qvhdl – contains the following:
• func_lib – functional simulation library lat_vhd needs to be compiled into this
directory.
• time_lib – timing simulation library lat_vitl needs to be compiled into this
directory.
• lsc_mod – module simulation library lsc_mod needs to be compiled into this
directory.
• options – options files required for functional and timing simulation.
■ vss – contains the following:
• func_lib – functional simulation library lat_vhd needs to be compiled into this
directory.
• time_lib – timing simulation library lat_vitl needs to be compiled into this
directory.
• lsc_mod – module simulation library lsc_mod needs to be compiled into this
directory.
• options – options files required for functional and timing simulation.
■ vantage – contains the following:
• func_lib – functional simulation library lat_vhd needs to be compiled into this
directory.
• options – options files required for functional and timing simulation.
VHDL Directory Structure
VHDL and Verilog Simulation User Manual 20
The VHDL Simulation Library Directory Structure on the PC Platform
The VHDL Simulation package contains source files and examples for functional and
timing (with or without VITAL acceleration) simulation. It also provides other vendor-
dependent option files required to compile and use the libraries.
The simulators supported on the PC platform are Model Technology V-System/VHDL
simulator and Viewlogic Speedwave. Figure 1-2 shows the directory structure for the
PC platform.

Figure 1-2. VHDL Simulation Library Directory Structure on PC Platforms
Examples Directory
The examples directory contains examples for each design environment:
■ modtech – contains files for Model Technology V-System
■ speedwav – contains files for Viewlogic SpeedWave
Each of the vendor subdirectories contains the following examples:
■ jkff – a JK flip-flop
■ traffic – a traffic light controller
■ multfifo – a module (FIFO-multiplier)
A step-by-step description is given for both functional and timing simulation using
either the “jkff” schematic design example or the “multfifo” example in Verilog or
VHDL design format.
<
ispcomp_vhdl
>
examples
library
modtech
src
speedwav
VHDL Directory Structure
VHDL and Verilog Simulation User Manual 21
Library Directory
The library directory contains five subdirectories. Many of the files are libraries that
need to be compiled into directories prior to running simulation. Please refer to the
appropriate simulator chapter for instructions on compiling the libraries for the
simulator you are using.
■ src – contains the following:
• Functional simulation library source file, func_src.vhd
• Timing simulation library source file, vital30.vhd

• Module simulation library source file, lscmod.vhd, for the ispLSI 6000 family
of devices
VHDL Simulation Libraries
VHDL and Verilog Simulation User Manual 22
VHDL Simulation Libraries
The VHDL simulation libraries are:
■ VHDL functional simulation library to support all devices. It consists of all the
primitives and macros for HDL design entry and pre-route functional simulation.
The source file is func_src.vhd.
■ VHDL timing simulation library to support all devices. It consists of all the timing
primitives for post-compilation timing simulation. The source file is vital30.vhd
for VITAL 3.0 compatibility.
■ VHDL module simulation library to support the 6000 family of devices. It
consists of the macros for both functional and timing simulation. The source file is
lscmod.vhd.
Before a library can be used for simulation, certain environment variables need to be
set up for each of the design environments. Once the variables are set, the libraries
can be compiled using the appropriate source file located in the
<
ispcomp_path
>/vhdl/library/src directory. Changes in the standard IEEE VHDL
packages also require recompilation of the VHDL simulation libraries.
A detailed explanation on setting up the environment and the steps for compiling in
each environment is described in each simulator-specific chapter.
VHDL Functional Simulation Library
The VHDL functional simulation library must be compiled using the func_src.vhd
file in the <
ispcomp_path
>/vhdl/library/src directory.
The VHDL functional simulation library contains behavioral and structural

descriptions of LSC primitives and macros. The library allows you to perform a
pre-route, unit-delay, functional simulation on VHDL designs. In the LSC design flow,
functional simulation is performed after your schematic or VHDL design is complete
and before it is compiled with the ispEXPERT Compiler software.
Although there are several ways to create the structural VHDL description, this
manual illustrates the method of converting a schematic design that uses LSC
macros into structural VHDL in the supported environments. Additionally, the LSC
VHDL libraries can be used with VHDL design files that make use of LSC macros.
VHDL Simulation Libraries
VHDL and Verilog Simulation User Manual 23
VHDL Timing Simulation Library
The VHDL timing simulation library must be compiled using the vital30.vhd file in
the <
ispcomp_path
>/vhdl/library/src directory.
Timing simulation can be performed on VHDL designs using VITAL (VHDL Initiative
Towards ASIC Libraries) and non-VITAL VHDL. While non-VITAL timing simulation is
supported on all environments, VITAL timing simulation is supported on all VITAL-
compliant VHDL simulators.
In the LSC design flow, timing simulation is performed after the design has been
compiled by the ispEXPERT Compiler software.
VHDL Module Simulation Library
The VHDL module simulation library must be compiled using the lscmod.vhd file in
the <
ispcomp_path
>/vhdl/library/src directory.
The VHDL module simulation library is required for both functional and timing
simulation of designs that use the 6000 family devices. The library allows you to
perform a pre-route, functional simulation on a module VHDL design. It also supports
post-route, timing simulation on the design after it is compiled with the ispEXPERT

Compiler.
In order to use an ispLSI 6000 family device, one or two of the VHDL module macro
configurations should be included in your design. The 25 macro configurations have
programmable features to be customized to your design. For details, refer to the
appropriate
ispEXPERT Compiler and “Third Party” Design Manual
.
In most cases, this library should not be used by itself. When running functional
simulation, both the VHDL module simulation library and the VHDL functional
simulation library should be used. When running timing simulation, the VHDL module
simulation library and the VHDL timing simulation library should be used.
VHDL Functional Simulation Overview
VHDL and Verilog Simulation User Manual 24
VHDL Functional Simulation Overview
Although there are several ways to create a design in VHDL, this manual uses two
approaches:
■ creating a design in Schematic Capture using the Lattice Schematic Library and
converting it into a VHDL structural netlist
■ creating a design in VHDL
The capture environment can be Cadence Concept, Mentor Graphics Design
Architect, and Viewlogic Viewdraw.
Convert the schematic into structural VHDL using the conversion utility in your design
environment. During this process, option files are required to ensure that VHDL
designs use the LSC VHDL libraries. These option files are available in the
<
ispcomp_path
>/vhdl/library/<
vendor
>/options directory. The result of the conversion
is the

design
.vhd file. Besides converting a schematic, you can create a VHDL
design file using LSC macros for Synopsys VSS, Cadence Leapfrog, and Model
Technology V-System.
Create your test bench/vectors for functional simulation. You can choose any method
to create a functional simulation test bench and observe your simulation outputs.
Compile your design.vhd file using the VHDL functional simulation library and the
test bench with your VHDL compiler. Once your design is compiled, perform the
functional simulation using the VHDL functional simulation library.
For designs using ispLSI 6000 family devices, the Lattice VHDL module simulation
library should also be used in design compilation and functional simulation.
VHDL Functional Simulation Overview
VHDL and Verilog Simulation User Manual 25
Functional Simulation Steps
The basic steps for functional simulation for a schematic design are:
1. Ensure that your environment is set up correctly. Refer to the chapter for your
simulator for information on environment setup.
2. Create a design in schematic capture using the LSC schematic library. If a design
is created in VHDL entry, skip steps 3 and 4.
3. Generate a symbol of your top-level schematic.
4. Convert your schematic design into a VHDL design file.
5. Create a work library for your VHDL design.
6. Compile your design.
7. Create a test bench and test vectors for your design.
8. Compile your simulation test bench/vectors.
9. Perform functional simulation.
The basic steps for functional simulation for a structural/behavioral design are:
1. Ensure that your environment is set up correctly. Refer to the chapter for your
simulator for information on environment setup.
2. Create a structural/behavioral VHDL design.

3. Create a work library for your VHDL design.
4. Compile your design.
5. Create a test bench and test vectors for your design.
6. Compile your simulation test bench/vectors.
7. Perform functional simulation.
The basic flow for functional simulation is shown in Figure 1-3.