đề cương ôn tập vhdl

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CÂU HỎI

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Câu 1: Thiết kế RS FF đồng bộ tín hiệu reset

1

Câu 2: Thiết kế RS FF không đồng bộ tín hiệu reset

2

Câu 3: Thiết kế JK FF không đồng bộ tín hiệu reset

3

Câu 4: Thiết kế JK FF đồng bộ tín hiệu reset

4

Câu 5: Thiết kế D FF không đồng bộ tín hiệu reset

5

Câu 6: Thiết kế D FF đồng bộ tín hiệu reset

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Câu 7: Thiết kế bộ đếm tiến theo mã nhị phân Kđ = 16

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Câu 8: Thiết kế bộ đếm lùi theo mã nhị phân Kđ = 10

8

Câu 9: Thiết kế bộ đếm lùi theo mã Gray Kđ = 16

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Câu 10: Thiết kế bộ đếm lùi theo mã Johnson 8 bít

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Câu 11:Thiết kế bộ đếm lùi

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Câu 12: Thiết kế mạch MUX 8-1

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Câu 13: Thiết kế mạch DEMUX 1-8

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Câu 14: Thiết kế mạch giải mã 7 đoạn

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Câu 15: Thiết kế mạch mã hóa thập phân ra Gray 4 bít

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Câu 16: Thiết kế T FF không đồng bộ tín hiệu reset

16

Câu 17: Thiết kế T FF đồng bộ tín hiệu reset

17

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Page 1

Câu 1: Thiết kế RS FF đồng bộ tín hiệu reset
// cach chon dang song tat ca chon clock
// CLk 20MHz R 10MHz S 5 Mhz RST 1 Mhz
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RSFFDBRst is
port(
R : in STD_LOGIC;
S : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC
);
end RSFFDBRst;

architecture RSFFDBRst of RSFFDBRst is
signal q0: std_logic;
begin
process
(CLK,RST,S,R)
variable RS:std_logic_vector (1 downto 0);
begin
RS:=R&S;
if (CLK' event and CLK='1') then
if (RST='1') then
q0<='0';
else
case RS is
when "00"=>q0<=q0;
when "01"=>q0<='1';
when "10"=>q0<='0';
when others=>q0<='X';
end case;
end if;
end if;
end process;
Q<=q0;
end RSFFDBRst;

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Page 2

// chay 10 us

Câu 2: Thiết kế RS FF không đồng bộ tín hiệu reset
// tat ca chon clock
// CLK 25Mhz R 20Mhz S 10 Mhz RST 1Mhz // chay 10us
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity RSFFKhongDBRst is
port(
R : in STD_LOGIC;
S : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC
);
end RSFFKhongDBRst;
architecture RSFFKhongDBRst of RSFFKhongDBRst is
signal q0: std_logic;
begin
process (CLK,RST,R,S)
variable RS:std_logic_vector (1 downto 0);
begin
RS:=R&S;
if (RST='1') then
q0<='0';
else if (CLK'event and CLK='1') then
case RS is
when "00"=>q0<=q0;
when "01"=>q0<='1';
when "10"=>q0<='0';
when others=>q0<='X';

end case;
end if;
end if;
end process;
Q<=q0;
end RSFFKhongDBRst;
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Page 3

Câu 3: Thiết kế JK FF không đồng bộ tín hiệu reset
// CLK 20M J 10M K 5M RST 1M chay 10us
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity JKFF is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;
Q : out STD_LOGIC
);
end JKFF;
architecture JKFF of JKFF is
signal Q0: std_logic;
begin
process(rst,clk,K,J)
variable JK:std_logic ( 1 downto 0);
begin

JK:=J&K;
if (rst='1') then
Q0:='0';
else

end if;
Trang

if (clk'event and clk='1') then
case JK is
when "00"=>Q0<=Q0;
when "01"=>Q0<='0';
when "10"=>Q0<='1';
when others =>Q0<=not(Q0);
end case;
end if;
end process;
Page 4

Câu 4: Thiết kế JK FF đồng bộ tín hiệu reset
// CLK 20M J 10M K 5M RST 1M chay 10us
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity JKFF is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
J : in STD_LOGIC;
K : in STD_LOGIC;

Q : out STD_LOGIC
);
end JKFF;
architecture JKFF of JKFF is
signal Q0: std_logic;
begin
process(rst,clk,K,J)
variable JK:std_logic ( 1 downto 0);
begin
JK:=J&K;
if (clk'event and clk='1') then
if (rst='1') then
Q0:='0';
else
case RS is
when "00"=>Q0<=Q0;
when "01"=>Q0<='0';
when "10"=>Q0<='1';
when others =>Q0<=not(Q0);
end case;
end if;
end if;
end process;
Q<=Q0;
end JKFF;
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Page 5

Câu 5: Thiết kế D FF không đồng bộ tín hiệu reset
//chon clock het CLk 20M
// D 10m RSt 1M chay 10us
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DFF is
port(
d : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC
);
end DFF;
architecture DFF of DFF is
begin
process(clk,rst,d)
begin
if(rst='1') then
q<='0';
else
if(clk'event and clk='1') then
q<=d;
end if;
end if;
end process;
end DFF;

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Page 6

Câu 6: Thiết kế D FF đồng bộ tín hiệu reset
//chon clock het CLk 20M
// D 10m RSt 1M chay 10us
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DFF is
port(
d : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC
);
end DFF;
architecture DFF of DFF is
begin
process(clk,rst,d)
begin
if(clk'event and clk='1') then
if(rst='1') then
q<='0';
else
q<=d;
end if;
end if;
end process;
end DFF;
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Page 7

Câu 7: Thiết kế bộ đếm tiến theo mã nhị phân Kđ = 16
// CLK chon clock 10M
// RST f(t) 0-0ns 1-150ns 0-350ns // chay 10us
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demkd16 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 downto 0)
);
end demkd16;
architecture demkd16 of demkd16 is
begin
process(clk,rst)
variable x:integer range 0 to 15;
begin
if (rst='1') then
x:=0;
else
if (clk'event and clk='1') then
if x=15 then
x:=0;
else
x:=x+1;
end if;
end if;

end if;
case x is
when 0 => Q<="0000";
when 1 => Q<="0001";
when 2 => Q<="0010";
when 3 => Q<="0011";
when 4 => Q<="0100";
when 5 => Q<="0101";
when 6 => Q<="0110";
when 7 => Q<="0111";
when 8 => Q<="1000";
when 9 => Q<="1001";
when 10 => Q<="1010";
when 11 => Q<="1011";
when 12 => Q<="1100";
when 13 => Q<="1101";
when 14 => Q<="1110";
when 15 => Q<="1111";
end case;
end process;
end demkd16;
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Page 8

Câu 8: Thiết kế bộ đếm lùi theo mã nhị phân Kđ = 10
// CLK chon clock 10M // RST chon f(t) 0-0ns 1-150ns 0-350ns // chay 10 us
library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity ok is
port(
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 downto 0) );
end ok;
architecture ok of ok is
begin
process (CLK,RST)
variable x: integer range 0 to 10;
begin
if (RST='1') then
x:=0;
else
if (CLK' event and CLK='1') then
if x=0 then
x:=10;
else
x:=x-1;
end if;
end if;
end if;
case x is
when 0 =>Q<="0000";
when 1 =>Q<="0001";
when 2 =>Q<="0010";
when 3 =>Q<="0011";
when 4 =>Q<="0100";
when 5 =>Q<="0101";
when 6 =>Q<="0110";

when 7 =>Q<="0111";
when 8 =>Q<="1000";
when others =>Q<="1001";
end case;
end process;
end ok;
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Page 9

Câu 9: Thiết kế bộ đếm lùi theo mã Gray Kđ = 16
// CLK chon clock 10M // RST chon f(t) 0-0ns 1-150ns 0-350ns // chay 10 us
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ok is
port(
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(3 downto 0) );
architecture ok of ok is
begin
process (CLK,RST)
variable x: integer range 0 to 15;
begin
if (RST='1') then
x:=0;
else
if (CLK' event and CLK='1') then
if x=0 then

x:=15;
else
x:=x-1;
end if;
end if;
end if;
case x is
when 0 =>Q<="0000";
when 1 =>Q<="0001";
when 2 =>Q<="0011";
when 3 =>Q<="0010";
when 4 =>Q<="0110";
when 5 =>Q<="0111";
when 6 =>Q<="0101";
when 7 =>Q<="0100";
when 8 =>Q<="1100";
when 9 =>Q<="1101";
when 10 =>Q<="1111";
when 11 =>Q<="1110";
when 12 =>Q<="1010";
when 13 =>Q<="1011";
when 14 =>Q<="1001";
when others =>Q<="1000";
end case;
end process;
end ok;
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Page 10

end ok;

Câu 10: Thiết kế bộ đếm lùi theo mã Johnson 8 bít
// CLK chon clock 10M // RST chon f(t) 0-0ns 1-150ns 0-350ns chay 10us
ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;
entity OK is
port(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(4 downto 0)
);
end OK;
architecture OK of OK is
begin
process (CLK, RST)
variable x: integer range 0 to 9;
begin
if (RST='1') then
x:=0;
else
if (CLK' event and CLk='1') then
if x=0 then
x:=9;
else
x:=x-1;
end if;
end if;
end if;

case x is
when 0 =>Q<= "00000";
when 1 =>Q<= "00001";
when 2 =>Q<= "00011";
when 3 =>Q<= "00111";
when 4 =>Q<= "01111";
when 5 =>Q<= "11111";
when 6 =>Q<= "11110";
when 7 =>Q<= "11100";
when 8 =>Q<= "11000";
when others =>Q<= "10000";
end case;
end process;
end OK;
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Page 11

Câu 11:Thiết kế bộ đếm lùi
//Xung:
Thay d?i n clk: 100MHz
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demluiKdbatky is
generic
(n:integer:=10);
port(
clk : in STD_LOGIC;
output : out integer range

);
end demluiKdbatky;

0 to n-1

architecture demluiKdbatky of demluiKdbatky is
begin
process(clk)
variable temp: integer range n-1 downto 0;
begin
if(clk'event and clk='1') then
temp:=temp-1;
if(temp=0) then
temp:=n-1;
end if;
end if;
output<=temp;
end process;
end demluiKdbatky;

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Page 12

Câu 12: Thiết kế mạch MUX 8-1
// S(2) chon clock 20M
// S(1) chon clock 10M
// S(0) chon clock 5M
// X chon Counter roi chon ma johnson 0.2 us

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DT4K13 is
port(
S : in STD_LOGIC_VECTOR(2 downto 0);
X : in STD_LOGIC_VECTOR(7 downto 0);
Y : out STD_LOGIC
);
end DT4K13;
architecture DT4K13 of DT4K13 is
begin
process (S,X)
begin
case S is
when "000" =>Y<= X(0);
when "001" =>Y<= X(1);
when "010" =>Y<= X(2);
when "011" =>Y<= X(3);
when "100" =>Y<= X(4);
when "101" =>Y<= X(5);
when "110" =>Y<= X(6);
when others =>Y<= X(7);
end case;
end process;
end DT4K13;

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Page 13

Câu 13: Thiết kế mạch DEMUX 1-8
//tat ca chon clock
// X 30M S(2) 20M S(1) 10M S(0) 5M
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Demux18 is
port(
X : in STD_LOGIC;
S : in STD_LOGIC_VECTOR(2 downto 0);
Y : out STD_LOGIC_VECTOR(7 downto 0)
);
end Demux18;
architecture Demux18 of Demux18 is
begin
process (S,X)
begin
if x='0' then Y<= ( others => '0' );
else
if S="000" then Y <= (0 => '1', others => '0');
elsif S="001" then Y <= (1 => '1', others => '0');
elsif S="010" then Y <= (2 => '1', others => '0');
elsif S="011" then Y <= (3 => '1', others => '0');
elsif S="100" then Y <= (4 => '1', others => '0');
elsif S="101" then Y <= (5 => '1', others => '0');
elsif S="110" then Y <= (6 => '1', others => '0');
else Y <= (7 => '1', others => '0');
end if;
end if;
end process;

end Demux18;

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Page 14

Câu 14: Thiết kế mạch giải mã 7 đoạn
// tat ca chon clock
// D(3) 40M D(2) 20M D(1) 10M D(0) 5M
// chay 10 us
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity BCDsang7doan is
port(
D : in STD_LOGIC_VECTOR(3 downto 0);
Y : out STD_LOGIC_VECTOR(6 downto 0)
);
end BCDsang7doan;
architecture BCDsang7doan of BCDsang7doan is
begin
process (D)
begin
case D is
when "0000" =>Y<= "1111110";
when "0001" =>Y<= "0110000";
when "0010" =>Y<= "1101101";
when "0011" =>Y<= "1111001";
when "0100" =>Y<= "0110011";

when "0101" =>Y<= "1011011";
when "0110" =>Y<= "1011111";
when "0111" =>Y<= "1110000";
when "1000" =>Y<= "1111111";
when "1001" =>Y<= "1111011";
when others =>Y<= "XXXXXXX";
end case;
end process;
end BCDsang7doan;

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Page 15

Câu 15: Thiết kế mạch mã hóa thập phân ra
Gray 4 bít
// d chon counter roi chon Circular one 100ns
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity thapphangray is
port(
D : in STD_LOGIC_VECTOR(9 downto 0);
G : out STD_LOGIC_VECTOR(3 downto 0)
);
end thapphangray;
architecture thapphangray of thapphangray is
begin
process (D)
begin

case D is
when "1000000000" =>G<="0000";
when "0100000000" =>G<= "0001";
when "0010000000" =>G<= "0011";
when "0001000000" =>G<= "0010";
when "0000100000" =>G<= "0110";
when "0000010000" =>G<= "0111";
when "0000001000" =>G<= "0101";
when "0000000100" =>G<= "0100";
when "0000000010" =>G<= "1100";
when others =>G<= "1101";
end case;
end process;

end thapphangray;

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Page 16

Câu 16: Thiết kế T FF không đồng bộ tín hiệu
reset
//chon clock het CLk 20M
// T 10m RSt 1M chay 10us
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TFFdongbo is
port(
T : in STD_LOGIC;

clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : buffer STD_LOGIC
);
end TFFdongbo;
architecture TFFdongbo of TFFdongbo is
begin
process
begin
wait until(clk' event and clk='1');
if(rst='1')then
q<='0';
else q<= not (q) ;
end if;
end process;
end TFFdongbo;

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Page 17

Câu 17: Thiết kế T FF đồng bộ tín hiệu reset
//chon clock het CLk 20M
// T 10m RSt 1M chay 10us
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity TFFkhongdongbo is
port(
T : in STD_LOGIC;

clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : buffer STD_LOGIC
);
end TFFkhongdongbo;
architecture TFFkhongdongbo of TFFkhongdongbo is
begin
process(rst,clk,T)
begin
if (rst='1') then q<='0';
elsif(clk' event and clk='1') then
q<= not (q);
end if;
end process;

end TFFkhongdongbo;

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Page 18

đề cương ôn tập vhdl

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