kiến trúc máy tính dạng thanh tin figs 3 the digital logic level sinhvienzone com
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3
THE DIGITAL LOGIC LEVEL
1
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+VCC
+VCC
+VCC
Vout
V1
Collector
Vout
Vout
Vin
V2
V1
V2
Emitter
Base
(a)
(b)
(c)
Figure 3-1. (a) A transistor inverter. (b) A NAND gate. (c) A NOR gate.
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NOT
A
X
A
NAND
X
B
A
0
1
X
1
0
(a)
NOR
A
X
B
A
0
0
1
1
B
0
1
0
1
(b)
X
1
1
1
0
AND
A
X
B
A
0
0
1
1
B
0
1
0
1
(c)
X
1
0
0
0
OR
A
X
B
A
0
0
1
1
B
0
1
0
1
X
0
0
0
1
(d)
A
0
0
1
1
B
0
1
0
1
X
0
1
1
1
(e)
Figure 3-2. The symbols and functional behavior for the five basic gates.
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A B C
A B C
A
1
A
4
5
B
ABC
ABC
2
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
(a)
M
0
0
0
1
0
1
1
1
8
B
6
ABC
C
3
C
7
ABC
(b)
Figure 3-3. (a) The truth table for the majority function of
three variables. (b) A circuit for (a).
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M
A
A
A
A
(a)
A
A
AB
A+B
B
B
A
AB
A
A+B
B
B
(b)
(c)
Figure 3-4. Construction of (a) NOT, (b) AND, and (c) OR
gates using only NAND gates or only NOR gates.
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AB
A
B
AB + AC
A
A(B + C)
B
AC
C
B+C
C
A
B
C
AB
AC
AB + AC
A
B
C
A
B+C
A(B + C)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
1
1
0
1
1
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(a)
(b)
Figure 3-5. Two equivalent functions. (a) AB + AC. (b) A(B + C).
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Name
AND form
OR form
Identity law
1A = A
0+A=A
Null law
0A = 0
1+A=1
Idempotent law
AA = A
A+A=A
Inverse law
AA = 0
A+A=1
Commutative law
AB = BA
A+B=B+A
Associative law
(AB)C = A(BC)
(A + B) + C = A + (B + C)
Distributive law
A + BC = (A + B)(A + C)
A(B + C) = AB + AC
Absorption law
A(A + B) = A
A + AB = A
De Morgan's law
AB = A + B
A + B = AB
Figure 3-6. Some identities of Boolean algebra.
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AB
=
A+B
A+B
(a)
AB
=
(c)
=
AB
(b)
A+B
A+B
=
AB
(d)
Figure 3-7. Alternative symbols for some gates: (a) NAND. (b) NOR.
(c) AND. (d) OR.
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A
A
B
XOR
0
0
0
0
1
1
1
0
1
A
1
1
0
B
B
(a)
(b)
A
A
B
B
A
A
B
B
(c)
(d)
Figure 3-8. (a) The truth table for the XOR function. (b)-(d)
Three circuits for computing it.
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A
B
F
A
B
F
A
B
F
0V
0V
0V
0
0
0
1
1
1
0V
5V
0V
0
1
0
1
0
1
5V
0V
0V
1
0
0
0
1
1
5V
5V
5V
1
1
1
0
0
0
(a)
(b)
(c)
Figure 3-9. (a) Electrical characteristics of a device.
(b) Positive logic. (c) Negative logic.
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VCC
14
13
12
11
10
9
8
1
2
3
4
5
6
7
Notch
GND
Figure 3-10. An SSI chip containing four gates.
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Pin 8
D0
D1
D2
D3
F
D4
D5
D6
D7
A A B B C C
A
B
C
Figure 3-11. An eight-input multiplexer circuit.
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VCC
D0
D0
D1
D1
D2
D2
D3
F
D4
D3
D5
D5
D6
D6
D7
D7
A B C
(a)
F
D4
A B C
(b)
Figure 3-12. (a) An MSI multiplexer.. (b) The same multiplexer wired to compute the majority function.
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D0
D1
A
B
A
D2
A
D3
B
D4
B
C
D5
C
C
D6
D7
Figure 3-13. A 3-to-8 decoder circuit.
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EXCLUSIVE OR gate
A0
B0
A1
B1
A=B
A2
B2
A3
B3
Figure 3-14. A simple 4-bit comparator.
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A
If this fuse is
blown, B is not
an input to AND
gate 1.
B
12 ϫ 2 = 24
input signals
L
24 input lines
0
1
49
0
1
6 outputs
If this fuse is
blown, AND gate
1 is not an input
to OR gate 5.
50 input
lines
5
Figure 3-15. A 12-input, 6-output programmable logic array.
The little squares represent fuses that can be burned out to
determine the function to be computed. The fuses are arranged
in two matrices: the upper one for the AND gates and the lower
one for the OR gates.
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D0
D1
D2
D3
D4
D5
D6
D7
S0
S1
S2
S3
S4
S5
S6
S7
C
Figure 3-16. A 1-bit left/right shifter.
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Exclusive OR gate
A
B
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Sum Carry
A
Sum
B
Carry
Figure 3-17. (a) Truth table for 1-bit addition. (b) A circuit for a half adder.
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Carry in
Carry
Carry
Sum
in
out
A
B
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
A
Sum
B
Carry out
(a)
(b)
Figure 3-18. (a) Truth table for full adder. (b) Circuit for a full adder.
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Logical unit
Carry in
AB
INVA
A
ENA
B
ENB
A+B
Output
B
Sum
Enable
lines
F0
Full
adder
F1
Decoder
Carry out
Figure 3-19. A 1-bit ALU.
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F1 F0
A7 B7
A6 B6
A5 B5
A4 B4
A3 B3
A2 B2
A1 B1
A0 B0
1-bit
ALU
1-bit
ALU
1-bit
ALU
1-bit
ALU
1-bit
ALU
1-bit
ALU
1-bit
ALU
1-bit
ALU
O7
O6
O5
O4
O3
O2
O1
O0
Carry
in
Carry
out
Figure 3-20. Eight 1-bit ALU slices connected to make an 8bit ALU. The enables and invert signals are not shown for simplicity.
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INC
C1
Delay
C2
(a)
(b)
A
B
C
(c)
Figure 3-21. (a) A clock. (b) The timing diagram for the
clock. (c) Generation of an asymmetric clock.
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S
0
1
Q
S
0
0
Q
1
1
R
0
0
0
0
(a)
Q
R
1
0
Q
A
B
NOR
0
0
1
0
1
0
1
0
0
1
1
0
(b)
(c)
Figure 3-22. (a) NOR latch in state 0. (b) NOR latch in state 1.
(c) Truth table for NOR.
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S
Q
Clock
Q
R
Figure 3-23. A clocked SR latch.
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D
Q
Q
Figure 3-24. A clocked D latch.
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