kiến trúc máy tính dạng thanh tin figs 6 the operating system machine level sinhvienzone com

6
THE OPERATING SYSTEM
MACHINE LEVEL

1

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Level 3

Operating system machine level
Operating system

Level 2

Instruction set architecture level
Microprogram or hardware

Level 1

Microarchitecture level

Figure 6-1. Positioning of the operating system machine level.

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Address space

Address

Mapping

8191
4096

4K Main
memory
4095
0

0
Figure 6-2. A mapping in which virtual addresses 4096 to
8191 are mapped onto main memory addresses 0 to 4095.

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Page

Virtual addresses

15

61440 – 65535

14

57344 – 61439

13

53248 – 57343

12

49152 – 53247

11

45056 – 49151

10

40960 – 45055

9

36864 – 40959

8

Bottom 32K of
main memory

32768 – 36863

Page

frame

Physical addresses

7

28672 – 32767

7

28672 – 32767

6

24576 – 28671

6

24576 – 28671

5

20480 – 24575

5

20480 – 24575

4

16384 – 20479

4

16384 – 20479

3

12288 – 16383

3

12288 – 16383

2

8192 – 12287

2

8192 – 12287

1

4096 – 8191

1

4096 – 8191

0

0 – 4095

0

0 – 4095

(a)

(b)

Figure 6-3. (a) The first 64K of virtual address space divided
into 16 pages, with each page being 4K. (b) A 32K main
memory divided up into eight page frames of 4K each.

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15-bit

Memory address

1 1 0 0 0 0 0 0 0 0 1 0 1 1 0

Output
register

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 0

Input
register

Virtual
page
Page
table
Present/absent
bit
15
14
13
12
11
10
9
8
7
6
5
4
3

1

110

2
1

0

20-bit virtual page

12-bit offset

32-bit virtual address

Figure 6-4. Formation of a main memory address from a virtual address.

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Page table
Virtual
page

Page
frame

15 0

0

14 1

4

13 0

0

12 0

0

11 1

5

10 0

0

9

0

0

Main memory

Page
frame

8

1

3

7

0

0

Virtual page 6

7

6

1

7

Virtual page 5

6

5

1

6

Virtual page 11 5

4

0

0

Virtual page 14 4

3

1

2

Virtual page 8

3

2

0

0

Virtual page 3

2

1

1

0

Virtual page 0

1

0

1

1

Virtual page 1

0

1 = Present in main memory
0 = Absent from main memory

Figure 6-5. A possible mapping of the first 16 virtual pages
onto a main memory with eight page frames.

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Virtual page 7

Virtual page 7

Virtual page 7

Virtual page 6

Virtual page 6

Virtual page 6

Virtual page 5

Virtual page 5

Virtual page 5

Virtual page 4

Virtual page 4

Virtual page 4

Virtual page 3

Virtual page 3

Virtual page 3

Virtual page 2

Virtual page 2

Virtual page 2

Virtual page 1

Virtual page 1

Virtual page 0

Virtual page 0

Virtual page 8

Virtual page 8

(a)

(b)

(c)

Figure 6-6. Failure of the LRU algorithm.

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Virtual address space
Free

Currently used

Call
stack

Address space
allocated to the
call stack

Parse
tree
Constant
table
Source
text
Symbol
table
Figure 6-7. In a one-dimensional address space with growing
tables, one table may bump into another.

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20K
16K
12K

Symbol
table

8K
Source
text

4K
0
Segment
0

Segment
1

Constant
table
Segment
2

Parse
tree
Segment
3

Call
stack

Segment
4

Figure 6-8. A segmented memory allows each table to grow or

shrink independently of the other tables.

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Consideration
Need the programmer be aware of it?
How many linear addresses spaces are there?
Can virtual address space exceed memory size?
Can variable-sized tables be handled easily?
Why was the technique invented?

Paging
No
1
Yes
No
To simulate large
memories

Segmentation
Yes
Many
Yes
Yes
To provide multiple
address spaces

Figure 6-9. Comparison of paging and segmentation.

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, ,

















,
,,

 ,
(3K)

(3K)

Segment 5
(4K)

Segment 5
(4K)

Segment 4
(7K)

Segment 4
(7K)

Segment 3
(8K)

Segment 3
(8K)

Segment 3
(8K)

Segment 2
(5K)

Segment 2
(5K)

Segment 2
(5K)

10K

(4K)

Segment 6

(4K)
Segment 2
(5K)

Segment 5
(4K)
Segment 6
(4K)

(3K)

(3K)

(3K)

Segment 2
(5K)

Segment 7
(5K)

Segment 7
(5K)

Segment 7
(5K)

Segment 7
(5K)

Segment 0
(4K)

Segment 0
(4K)

Segment 0
(4K)

Segment 0
(4K)

Segment 0
(4K)

(a)

(b)

(c)

(d)

(e)

Segment 1
(8K)

Figure 6-10. (a)-(d) Development of external fragmentation
(e) Removal of the external fragmentation by compaction.

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Descriptor
Page frame

Descriptor
segment

Segment
number

Page
number

Word

Page
table

Offset
Page

18-Bit Segment
number

6-Bit page
number

10-Bit offset
within the page

Two-part MULTICS address

Figure 6-11. Conversion of a two-part MULTICS address into
a main memory address.

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Bits

13

1 2

INDEX
0 = GDT
1 = LDT

Privilege level (0-3)

Figure 6-12. A Pentium II selector.

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Relative
address
0

32 Bits
BASE 0-15
BASE 24-31 G D 0

0 : LIMIT is in bytes
1 : LIMIT is in pages
0 : 16-bit segment
1 : 32-bit segment

LIMIT
LIMIT 16-19 P DPL

TYPE

BASE 16-23

4

Segment type and protection
Privilege level (0-3)
0 : Segment is absent from memory
1 : Segment is present from memory

Figure 6-13. A Pentium II code segment descriptor. Data segments differ slightly.

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Selector

Offset
Descriptor
Base address

+

Limit
Other fields

32-bit linear address
Figure 6-14. Conversion of a (selector, offset) pair to a linear address.

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Bits

10

Linear address
10

12

DIR

PAGE

OFF

(a)
Page directory

Page table

Page frame

Word selected
PAGE

DIR

OFF
(b)

Figure 6-15. Mapping of a linear address onto a physical address.

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User programs

Possible uses of
the levels

ared libraries
Sh
stem calls
y
S

Kernel
0
1
2
3
Level
Figure 6-16. Protection on the Pentium II.

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Bits

51

13

Virtual
8K Virtual
address page number Offset

Physical
address
Bits

8K Page
frame

Offset

28

13

48

16

45

19

42

512K Virtual
page number Offset

4M Virtual
page number Offset

64K Page
Offset
frame

512K Page
Offset
frame

4M Page
Offset
frame

25

16

22

19

19

Figure 6-17. Virtual to physical mappings on the UltraSPARC.

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22

64K Virtual
page number Offset

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22


TSB (MMU + sofware)

TLB (MMU hardware)
Context
Flags
Virtual
page Physical
page
Valid

Context
Virtual
Flags
page
Physical
tag
page
Valid

Translation table
(Operating system)

(a)

Entry 0 is shared

by all virtual pages
ending in 0…0000

Entry 1 is shared
by all virtual pages
ending in 0…0001

Format is
entirely
defined by
the operating
system

(b)
(c)

Figure 6-18. Data structures used in translating virtual addresses on the UltraSPARC. (a) TLB. (b) TSB. (c) Translation
table.

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Logical
record
number

14

15

1 logical
record

15
16

17

Next logical
record to be
read

17
18

16

18
19

19

20

20

21

21

22

Main memory

22

Next logical
record to be
read

Main memory

23
Logical
record 18

23

Buffer

24

24

25

25

26

(a)

Logical
record 19

(b)

Figure 6-19. Reading a file consisting of logical records. (a)
Before reading record 19. (b) After reading record 19.

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Buffer


Sector 11

Sector
1

Sector
1

5

4

2

1

3

Track 0

3

1

0

Track 4

Sector 0

6

12
0

11

1

Sector 11

Sector 0

1

7

1

1

6

5

9

3

9
7

4

12

Read/
write
head

10
14

13

Direction
of disk
rotation

Direction
of disk
rotation

(a)

(b)

Figure 6-20. Disk allocation strategies. (a) A file in consecutive sectors. (b) A file not in consecutive sectors.

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8

14
2

8

Read/
write
head

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Track Sector Number of
sectors
in hole
0
0
1
1
2
2
2
3
3
4

0
6
0
11
1
3
7
0
9
3

5
6
10
1

1
3
5
3
3
8

Track 0
0
1
2
3
4

0
0
1
0
1

1

2

3

4

Sector
5 6 7

8

9 10 11

0
0
0
0
1

0
0
1
0
1

0
0
0
1
0

0
0
0
1
0

1

0
0
1
0

0
0
0
1
0

0
0
0
1
0

0
0
0
0
0

0
0
1
1
0
(b)

(a)

Figure 6-21. Two ways of keeping track of available sectors.
(a) A free list. (b) A bit map.

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0
1
0
0
0

0
0
0
0
1


File 0

File name:

Rubber-ducky

File 1

Length:

1840

File 2

Type:

Anatidae dataram

File 3

Creation date:

March 16, 1066

File 4

Last access:

September 1, 1492

File 5

Last change:

July 4, 1776

File 6

Total accesses: 144

File 7

Block 0:

Track 4

Sector 6

File 8

Block 1:

Track 19

Sector 9

File 9

Block 2:

Track 11

Sector 2

File 10

Block 3:

Track 77

Sector 0

Figure 6-22. (a) A user file directory. (b) The contents of a
typical entry in a file directory.

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Process 3 waiting for CPU
Process 3
Process 3
Process 2
Process 2
Process 1
Process 1
Process 1 running
Time

Time

(a)

(b)

Figure 6-23. (a) True parallel processing with multiple CPUs.
(b) Parallel processing simulated by switching one CPU among
three processes.

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In

In
Out

In

In
Out

In,
out

Out

In

Out

Out
(a)

(b)

(c)

(d)

(e)

Figure 6-24. Use of a circular buffer.

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(f)