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Computer Architecture
Structured Computer Organization
by A. Tanenbaum, Prentice Hall, 2005

B. W. Wah
ECE 290
Fall 2006

Introductions

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Languages, Levels, Virtual Machines

A multilevel machine
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Contemporary Multilevel Machines

A six-level computer.
The support method for each level is indicated below it .

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Computer Generations
•

Zero’th Generation
Mechanical Computers (1642 – 1945)

•

First Generation
Vacuum Tubes (1945 – 1955)

•

Second Generation
Transistors (1955 – 1965)

•

Third Generation
Integrated Circuits (1965 – 1980)

•

Fourth Generation
Very Large Scale Integration (1980 – ?)

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Von Neumann Machine

The original Von Neumann machine.
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PDP-8 Innovation – Single Bus

The PDP-8 omnibus
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Technological and Economic Forces

Moore’s law predicts a 60-percent annual increase in the
number of transistors that can be put on a chip.
The data points given in this figure are memory sizes, in bits.
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Personal Computer
1. Pentium 4 socket
2. 875P Support chip
3. Memory sockets
4. AGP connector
5. Disk interface
6. Gigabit Ethernet
7. Five PCI slots
8. USB 2.0 ports
9. Cooling technology
10. BIOS
A printed circuit board is at the heart of every personal computer. This
figure is a photograph of the Intel D875PBZ board. The photograph is
copyrighted by the Intel Corporation, 2003 and is used by permission.
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Example Computer Families
•
•
•

Pentium 4 by Intel
UltraSPARC III by Sun Microsystems
The 8051 chip by Intel, used for embedded systems

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Intel Computer Family (1)

The Intel CPU family. Clock speeds are measured in MHz
(megahertz) where 1 MHZ is 1 million cycles/sec.
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Intel Computer Family (2)

The Pentium 4 chip. The photograph is copyrighted by the Intel
Corporation, 2003 and is used by permission.
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Intel Computer Family (3)

Moore’s law for (Intel) CPU chips.
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Computer Systems Organization

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Central Processing Unit

The organization of a simple computer with
one CPU and two I/O devices
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CPU Organization

The data path of a typical Von Neumann machine.
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Instruction Execution Steps
1.
2.
3.
4.
5.
6.

Fetch next instruction from memory into instr. register
Change program counter to point to next instruction
Determine type of instruction just fetched
If instructions uses word in memory, determine where
Fetch word, if needed, into CPU register
Execute the instruction
Go to step 1 to begin executing following instruction

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RISC versus CISC
• 1980: RISC has simple instructions that can be executed in
one cycle of a simple data path
• Execute frequently used instructions efficiently and less frequently
used instructions less efficiently
• Wins over CISC that takes multiple and longer cycles to execute a
complex instruction
• May take 4-5 instructions to accomplish a complex operation

• CISC is still predominant in today’s market
• Backward compatibility to early CISC computers

• Starting with 486, Intel CPUs contain a RISC core that executes the
simplest (and typically most common) instructions in a single data
path cycle, while interpreting the more complicated instructions in
the usual CISC way
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Design Principles for Modern Computers
•
•
•
•
•

All instructions directly executed by hardware
Maximize rate at which instructions are issued
Instructions should be easy to decode
Only loads, stores should reference memory
Provide plenty of registers

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Instruction-Level Parallelism

a)
b)

A five-stage pipeline
The state of each stage as a function of time. Nine clock
cycles are illustrated
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Superscalar Architectures (1)

Dual five-stage pipelines with a common instruction fetch unit.
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Superscalar Architectures (2)

A superscalar processor with five functional units.
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Processor-Level Parallelism (1)

An array of processor of the ILLIAC IV type.
(ILLIAC I in Sept. 1952)
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Processor-Level Parallelism (2)

a)
b)

A single-bus multiprocessor.
A multicomputer with local memories.
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Cache Memory

The cache is logically between the CPU and main
memory. Physically, there are several possible places it
could be located.
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Memory Hierarchies

A five-level memory hierarchy.
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Magnetic Disks (1)

A portion of a disk track. Two sectors are illustrated.
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Magnetic Disks (2)

A disk with four platters.
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Magnetic Disks (3)

A disk with five zones. Each zone has many tracks
and has uneven number of tracks across zones.
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RAID (1)
Redundant Array of Inexpensive Disks (1988)

4 bit with error
correction in CM2

RAID levels 0 through 2.
Backup and parity disks are shown shaded.
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RAID (1)
Redundant Array of Inexpensive Disks

RAID levels 3 through 5.
Backup and parity disks are shown shaded.
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The Processor Level

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CPU Chips

The logical pinout of a generic CPU. The arrows indicate input
signals and output signals. The short diagonal lines indicate
that multiple pins are used. For a specific CPU, a number will
be given to tell how many.
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Computer Buses (1)

A computer system with multiple buses.
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Computer Buses (2)

Examples of bus masters and slaves.
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Bus Width

Growth of an Address bus over time.
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Bus Clocking

Read timing on a synchronous bus.
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Asynchronous Buses

Operation of an asynchronous bus.
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Bus Arbitration (1)

(a) A centralized one-level bus arbiter using daisy chaining.
(b) The same arbiter, but with two levels.
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Bus Arbitration (2)

Decentralized bus arbitration.
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Bus Operations (1)

A block transfer.
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Bus Operations (2)

Use of the 8259A interrupt controller.

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The Pentium 4

The Pentium 4 physical pinout.
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The Pentium 4’s Logical Pinout
Logical pinout of
the Pentium 4.
Names in upper
case are the
office are the
official Intel
names for
individual signals.
Names in mixed
case are groups
of related signals
or signal
descriptions.
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Pipelining on the Pentium 4’s Memory Bus

Pipelining requests on the Pentium 4’s memory bus.
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The UltraSPARC III (1)

The UltraSPARC III CPU chip.
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The UltraSPARC III (2)

The main features of the core of an UltraSPARC III system.
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The PCI Bus (1)

Architecture of an early Pentium system. The thicker buses have more
bandwidth than the thinner ones but the figure is not to scale.
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The PCI Bus (2)

The bus structure of a modern Pentium 4.
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PCI Bus Arbitration

The PCI bus uses a centralized bus arbiter.
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