Lecture Digital logic design - Lecture 25: Shift registers

Lecture 25

Shift Registers

1


Overvie
w
° Multiple flip flops can be combined to form a data
register
° Shift registers allow data to be transported one bit at a
time
° Registers also allow for parallel transfer
• Many bits transferred at the same time

° Shift registers can be used with adders to build
arithmetic units
° Remember: most digital hardware can be built from
combinational logic (and, or, invert) and flip flops
• Basic components of most computers

2


Reg
iste
°rRegister: Group of Flip-Flops
with
°Par
Ex: D Flip-Flops

allel
°Loa
Holds a Word (Nibble) of Data
°dLoads in Parallel on Clock
Transition
° Asynchronous Clear (Reset)

3


Reg
iste
The transfer of new information into a register is referred to as loading the register
r
All the bits of the register are loaded simultaneously with a single clock pulse, the loading is parallel
with
CP input acts as an enable signal that controls the
Par
loading of new information into the register. When
CP goes to 1, the input information is loaded into
allel
the register. If CP remains at 0, the content of the
Loa
register is not changed.
d
The load input goes through a buffer gate (to
reduce loading) and through a series of
AND gates to the Rand S inputs of each flip-flop.
Although

If the load input is 0, both R and S are 0, and
no change of state occurs with any
clock pulse.

For each I that is equal to 1, the corresponding flip-flop
inputs are S = 1, R = 0.
For each I that is equal to 0, the corresponding flip-flop
inputs are S = 0, R = 1.
Thus, the input value is transferred into the register
provided the load input is 1 and the clear input is4 1


Reg
iste
°r Load Control = 1
with
• New data loaded
Loa
on next positive
d clock edge
Con
°trol
Load Control = 0
• Old data reloaded
on next positive
clock edge

The feedback connection in each flip-flop is
necessary when a D type is used because a D
flip-flop does not have a "no change"

input condition.

5


Sequential-Logic Implementation
Since
registers
are
readily available as MSI
circuits,
it
becomes
convenient at times to
employ a register as part
of the sequential circuit.
The present state of the
register and the external
inputs determine the next
state of the register and
the values of external
outputs
Part of the combinational circuit determines the
next state and the other part generates the outputs.
The next state value from the combinational circuit
is loaded into the register with a clock pulse.

If the register has a load input, it must be set to I; otherwise, if the register has no
load input, the next state value will be transferred automatically every clock pulse.

6


Example
Design the sequential circuit whose state table is listed in Fig. The state table specifies two
flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information
is obtained directly from the table:

7


Example
Design the sequential circuit whose state table is listed in Fig. The state table specifies two
flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information
is obtained directly from the table:

8


Example
Design the sequential circuit whose state table is listed in Fig. The state table specifies two
flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information
is obtained directly from the table:

9


Example
Design the sequential circuit whose state table is listed in Fig. The state table specifies two
flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information

is obtained directly from the table:

10


Example
Design the sequential circuit whose state table is listed in Fig. The state table specifies two
flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information
is obtained directly from the table:

11


Example
Design the sequential circuit whose state table is listed in Fig. The state table specifies two
flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information
is obtained directly from the table:

12


Example
Design the sequential circuit whose state table is listed in Fig. The state table specifies two
flip-flops, A1 and A2; one input, x; and one output, y. The next-state and output information
is obtained directly from the table:

13


Shif

t
°Reg
Cascade chain of Flip-Flops
iste
°rs
Bits travel on Clock edges
° Serial in – Serial out, can also have parallel load /
read

14


Serial Transfer

15


Serial Transfer

16


Parallel Data Transfer
° All data transfers on rising clock edge
° Data clocked into register Y

17


Par

allel
ver
° sus
Serial communications is defined as
Seri
• Provides a binary number as a sequence of binary digits, one
al after another, through one data line.
° Parallel communications
• Provides a binary number through multiple data lines at the
same time.

18


Shif
t
°regi
Parallel-to-serial conversion for serial transmission
ster
appl
icati
on
parallel outputs

parallel inputs

serial transmission

19

Serial Transfer of
Data
° Transfer from register X to register Y (negative
clock edges for this example)

20


Patt
ern
° Combinational
function of input samples
rec
• in this case, recognizing the pattern 1001 on the single input
ognsignal
izer

OUT

OUT1
IN

D Q

D Q

OUT2
D Q

OUT3

OUT4

D Q

CLK

Clk             IN  OUT1  OUT2  OUT3  OUT4  OUT
Before                                                           
1                  1       0           0            0           0            0 
2                  0       1           0            0           0            0 
3                  0       0           1            0           0            0 
4                  1       0           0            1           0            0 
5
       0       1           0            0           1            1

21


Patt
ern
° Combinational
function of input samples
rec
• in this case, recognizing the pattern 100011 on the single input
ognsignal
izer
• 6 flip-Flops are required
• 7 clock pulses

22


Seri
al
°Add
Slower than
itio
parallel
n (D
°Flip
Low cost
°Flo
Share fast
hardware on
p)slow data
° Good for
multiplexed
data

23


Seri
al
Add
° Only
one full
itio

adder
n (D
° Reused
Flip
for
each
bit
Flo
° Start
with lowp)
order bit
addition
° Note that carry
(Q) is saved
° Add multiple
values.
• New values
placed in shift
register B
24


Seri
al
Add
itio
n (D
Flip
Flo
p)

° Shift control used to
stop addition
° Generally not a good
idea to gate the clock
° Shift register can be
arbitrary length
° FA can be built from
combin. logic
25