Behavioral Modeling

CHAPTER
2
Behavioral
Modeling
In Chapter 1, we discussed different modeling techniques
and touched briefly on behavioral modeling. In this chapter,
we discuss behavioral modeling more thoroughly, as well
as some of the issues relating to the simulation and syn-
thesis of VHDL models.
2
Chapter Two
16
Introduction to Behavioral
Modeling
The signal assignment statement is the most basic form of behavioral
modeling in VHDL. Following is an example:
a <= b;
This statement is read as follows:
a
gets the value of
b
. The effect of
this statement is that the current value of signal
b
is assigned to signal
a
. This statement is executed whenever signal
b
changes value. Signal
b
is in the sensitivity list of this statement. Whenever a signal in the sen-

sitivity list of a signal assignment statement changes value, the signal
assignment statement is executed. If the result of the execution is a new
value that is different from the current value of the signal, then an event
is scheduled for the target signal. If the result of the execution is the same
value, then no event is scheduled but a transaction is still generated
(transactions are discussed in Chapter 3, “Sequential Processing”). A trans-
action is always generated when a model is evaluated, but only signal
value changes cause events to be scheduled.
The next example shows how to introduce a nonzero delay value for the
assignment:
a <= b after 10 ns;
This statement is read as follows:
a
gets the value of
b
when 10
nanoseconds of time have elapsed.
Both of the preceding statements are concurrent signal assignment state-
ments. Both statements are sensitive to changes in the value of signal
b
.
Whenever
b
changes value, these statements execute and new values are
assigned to signal
a
.
Using a concurrent signal assignment statement, a simple AND gate
can be modeled, as follows:
ENTITY and2 IS

PORT ( a, b : IN BIT;
PORT ( c : OUT BIT );
END and2;
ARCHITECTURE and2_behav OF and2 IS
BEGIN
c <= a AND b AFTER 5 ns;
17
Behavioral Modeling
A
B
C
Figure 2-1
AND Gate Symbol.
END and2_behav;
The AND gate has two inputs
a, b
and one output
c
, as shown in Figure
2-1. The value of signal
c
may be assigned a new value whenever either
a
or
b
changes value. With an AND gate, if
a
is a
‘0’
and

b
changes from a
‘1’
to a
‘0’
, output
c
does not change. If the output does change value, then
a transaction occurs which causes an event to be scheduled on signal
c
;
otherwise, a transaction occurs on signal
c
.
The entity design unit describes the ports of the
and2
gate. There are
two inputs
a
and
b
, as well as one output
c
. The architecture
and2_behav
for entity
and2
contains one concurrent signal assignment statement. This
statement is sensitive to both signal
a

and signal
b
by the fact that the
expression to calculate the value of
c
includes both
a
and
b
signal values.
The value of the expression
a
and
b
is calculated first, and the resulting
value from the calculation is scheduled on output
c
, 5 nanoseconds from
the time the calculation is completed.
The next example shows more complicated signal assignment state-
ments and demonstrates the concept of concurrency in greater detail. In
Figure 2-2, the symbol for a four-input multiplexer is shown.
This is the behavioral model for the mux:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY mux4 IS
PORT ( i0, i1, i2, i3, a, b : IN std_logic;
PORT ( i0, i1, i2, i3, a, q : OUT std_logic);
END mux4;
ARCHITECTURE mux4 OF mux4 IS

SIGNAL sel: INTEGER;
BEGIN
WITH sel SELECT
q <= i0 AFTER 10 ns WHEN 0,
q <= i1 AFTER 10 ns WHEN 1,
Chapter Two
18
I0
I1
A B
Q
MUX4
I3
I2
Figure 2-2
Mu
x
4 Symbol.
q <= i2 AFTER 10 ns WHEN 2,
q <= i3 AFTER 10 ns WHEN 3,
q <= ‘X’ AFTER 10 ns WHEN OTHERS;
sel <= 0 WHEN a = ‘0’ AND b = ‘0’ ELSE
1 WHEN a = ‘1’ AND b = ‘0’ ELSE
2 WHEN a = ‘0’ AND b = ‘1’ ELSE
3 WHEN a = ‘1’ AND b = ‘1’ ELSE
4 ;
END mux4;
The entity for this model has six input ports and one output port. Four
of the input ports (
I0

,
I1
,
I2
,
I3
) represent signals that will be assigned
to the output signal
q
. Only one of the signals will be assigned to the out-
put signal
q
based on the value of the other two input signals
a
and
b
. The
truth table for the multiplexer is shown in Figure 2-3.
To implement the functionality described in the preceding, we use a
conditional signal assignment statement and a selected signal assignment.
The second statement type in this example is called a conditional signal
assignment statement. This statement assigns a value to the target sig-
nal based on conditions that are evaluated for each statement. The
statement
WHEN
conditions are executed one at a time in sequential order
until the conditions of a statement are met. The first statement that
matches the conditions required assigns the value to the target signal.
The target signal for this example is the local signal
sel

. Depending
on the values of signals
a
and
b
, the values 0 through 4 are assigned
to
sel
.
If more than one statement’s conditions match, the first statement that
19
Behavioral Modeling
ABQ
00I0
10I1
01I2
11I3
Figure 2-3
Mux Functional
Table.
matches does the assign, and the other matching statements’ values are
ignored.
The first statement is called a selected signal assignment and selects
among a number of options to assign the correct value to the target sig-
nal. The target signal in this example is the signal
q
.
The expression (the value of signal
sel
in this example) is evaluated,

and the statement that matches the value of the expression assigns the
value to the target signal. All of the possible values of the expression must
have a matching choice in the selected signal assignment (or an
OTHERS
clause must exist).
Each of the input signals can be assigned to output
q
, depending on the
values of the two select inputs,
a
and
b
. If the values of
a
or
b
are unknown
values, then the last value, ‘X’ (unknown), is assigned to output
q
. In this
example, when one of the select inputs is at an unknown value, the out-
put is set to unknown.
Looking at the model for the multiplexer, it looks like the model will
not work as written. It seems that the value of signal
sel
is used before
it is computed. This impression is received from the fact that the second
statement in the architecture is the statement that actually computes the
value for
sel

. The model does work as written, however, because of the
concept of concurrency.
The second statement is sensitive to signals
a
and
b
. Whenever either
a
or
b
changes value, the second statement is executed, and signal
sel
is
updated. The first statement is sensitive to signal
sel
. Whenever signal
sel
changes value, the first signal assignment is executed.
If this example is processed by a synthesis tool, the resulting gate
structure created resembles a 4 to 1 multiplexer. If the synthesis library
contains a 4 to 1 multiplexer primitive, that primitive may be generated
Chapter Two
20
based on the sophistication of the synthesis tool and the constraints put
on the design.
Transport Versus Inertial Delay
In VHDL, there are two types of delay that can be used for modeling
behaviors. Inertial delay is the most commonly used, while transport delay
is used where a wire delay model is required.
Inertial Delay

Inertial delay is the default in VHDL. If no delay type is specified, iner-
tial delay is used. Inertial delay is the default because, in most cases, it
behaves similarly to the actual device.
In an inertial delay model, the output signal of the device has inertia,
which must be overcome for the signal to change value. The inertia value
is equal to the delay through the device. If there are any spikes, pulses,
and so on that have periods where a signal value is maintained for less
than the delay through the device, the output signal value does not
change. If a signal value is maintained at a particular value for longer
than the delay through the device, the inertia is overcome and the device
changes to the new state.
Figure 2-4 is an example of a very simple buffer symbol. The buffer has
a single input A and a single output B. The waveforms are shown for input
A and the output B. Signal A changes from a
‘0’
to a
‘1’
at 10 nanoseconds
and from a
‘1’
to a
‘0’
at 20 nanoseconds. This creates a pulse or spike
that is 10 nanoseconds in duration. The buffer has a 20- nanosecond delay
through the device.
The
‘0’
to
‘1’
transition on signal A causes the buffer model to be exe-

cuted and schedules an event with the value
‘1’
to occur on output B at
time 30 nanoseconds. At time 20 nanoseconds, the next event on signal A
occurs. This executes the buffer model again. The buffer model predicts a
new event on output B of a
0
value at time 40 nanoseconds. The event
scheduled on output B for time 30 nanoseconds still has not occurred. The
new event predicted by the buffer model clashes with the currently
scheduled event, and the simulator preempts the event at 30 nanoseconds.
The effect of the preemption is that the spike is swallowed. The reason
for the cancellation is that, according to the inertial delay model, the first
21
Behavioral Modeling
A
B
0
10 20 30 40
AB
Delay = 20 ns
Figure 2-4
Inertial Delay Buffer
Waveforms.
event at 30 nanoseconds did not have enough time to overcome the inertia
of the output signal.
The inertial delay model is by far the most commonly used in all cur-
rently available simulators. This is partly because, in most cases, the
inertial delay model is accurate enough for the designer’s needs. One
more reason for the widespread use of inertial delay is that it prevents

prolific propagation of spikes throughout the circuit. In most cases, this
is the behavior wanted by the designer.
Transport Delay
Transport delay is not the default in VHDL and must be specified. It repre-
sents a wire delay in which any pulse, no matter how small, is propagated
to the output signal delayed by the delay value specified. Transport delay
is especially useful for modeling delay line devices, wire delays on a PC
board, and path delays on an ASIC.
If we look at the same buffer circuit that was shown in Figure 2-4, but
replace the inertial delay waveforms with the transport delay waveforms,
we get the result shown in Figure 2-5. The same waveform is input to
signal A, but the output from signal B is quite different. With transport
delay, the spikes are not swallowed, but the events are ordered before
Chapter Two
22
AB
Delay = 20 ns
A
B
0
10 20 30 40
Figure 2-5
Transport Delay
Buffer Waveforms.
propagation.
At time 10 nanoseconds, the buffer model is executed and schedules an
event for the output to go to a 1 value at 30 nanoseconds. At time 20
nanoseconds, the buffer model is re-invoked and predicts a new value for
the output at time 40 nanoseconds. With the transport delay algorithm,
the events are put in order. The event for time 40 nanoseconds is put in

the list of events after the event for time 30 nanoseconds. The spike is not
swallowed but is propagated intact after the delay time of the device.
Inertial Delay Model
The following model shows how to write an inertial delay model. It is
the same as any other model we have been looking at. The default delay
type is inertial; therefore, it is not necessary to specify the delay type to
be inertial:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY buf IS
PORT ( a : IN std_logic;
PORT ( b : OUT std_logic);
END buf;
23
Behavioral Modeling
ARCHITECTURE buf OF buf IS
BEGIN
b <= a AFTER 20 ns;
END buf;
Transport Delay Model
Following is an example of a transport delay model. It is similar in every
respect to the inertial delay model except for the keyword
TRANSPORT
in
the signal assignment statement to signal
b
. When this keyword exists,
the delay type used in the statement is the transport delay mechanism:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY delay_line IS
PORT ( a : IN std_logic;
PORT ( b : OUT std_logic);
END delay_line;
ARCHITECTURE delay_line OF delay_line IS
BEGIN
b <= TRANSPORT a AFTER 20 ns;
END delay_line;
Simulation Deltas
Simulation deltas are used to order some types of events during a simu-
lation. Specifically, zero delay events must be ordered to produce con-
sistent results. If zero delay events are not properly ordered, results can
be disparate between different simulation runs. An example of this is
shown using the circuit shown in Figure 2-6. This circuit could be part of
a clocking scheme in a complex device being modeled. It probably would
not be the entire circuit, but only a part of the circuit used to generate
the clock to the D flip-flop.
The circuit consists of an inverter, a NAND gate, and an AND gate
driving the clock input of a flip-flop component. The NAND gate and AND
gate are used to gate the clock input to the flip-flop.
Let’s examine the circuit operation, using a delta delay mechanism and
another mechanism. By examining the two delay mechanisms, we will
better understand how a delta delay orders events.