lenovo 047ad compal LA b211p r1 0 20141

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Model Name : Z5WAL
File Name : LA-B211P

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Compal Confidential
2

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EA51_BM UMA M/B Schematics Document
Intel Bay Trail M

2014-04-07
REV:1.0

3

3

Panelization Information
LA-B211P
Main Board
PWR Board
LS-B161P
USB Board
LS-B162P
BATT Board
LS-B163P

4

4

PCB@
ZZZ
PCB Z5WAL LA-B211P LS-B161P/B162P/B163P

Part Number
DAZ15Y00100

Description
PCB Z5WAL LA-B211P LS-B161P/B162P/B163P

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

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Cover Page

Z5WAL_Bay Trail M_LA‐B211P

Sheet

Monday, April 07, 2014

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eDP Conn.

HDMI Conn.

204pin DDR3L-SO-DIMM X1

1

1

P.13
P.16

P.15

port 0

port 1

Memory BUS

204pin DDR3L-SO-DIMM X1

Dual Channel

P.14

1.35V DDR3L 1066/1333

DDI x2

CRT Conn.
VGA x1

USB2.0 x4

P.17

PCIE II x1

LAN(GbE) / Card Reader
RTL8411B

PCIE II x1

FCBGA 1170 Pin

port 2

USB HUB
GL850G

P.21

USB 3.0
Conn P.21

SOC

P.18,19

port 1

USB3.0 x1

port 0

RJ45 Conn.

2

VALLEYVIEW-M

port 0

port 3

HD Camera
Conn.

Touch Panel
Conn.

P.15

P.15

2

HUB port1

MINI CARD
WLAN/BT

port 1

P.19

Card Reader
2 in 1(SD)
SATA II x2
P.20

port 1

HD Audio

P.20

HDA Codec

page 05~12

port 0
LPC BUS

ALC283

P.24

SPI

3

3

EC
ENE KB9022

SATA ODD Conn.
RTC CKT.
P.08

Power Circuit DC/DC
P.26~P.34

4

LED/Power On/Off
P.23

P.23

Universal Jack

P.24

P.24

Int. MIC
P.24

P.08

P.23

Sub Board
Touch Pad
PS2/I2C

LS_B161P PWR

Int.KBD

LS_B162P USB
HUB port2,3

4

LS_B163P BATT

Fan Control

Speaker

P.22

SATA HDD Conn.

DC/DC Interface CKT.
P.25

SPI ROM
1.8V (8MB)

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

P.20

2013/04/12

2014/04/12

Deciphered Date

Title

Block Diagrams

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

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Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

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Board ID / SKU ID Table for AD channel
Vcc
Ra/Rc/Re
Board ID

Voltage Rails
Power Plane
1

2

S0

S3

S4/S5

VIN

19V Adapter power supply

Description

ON

ON

ON

BATT+

12V Battery power supply

ON

ON

ON

B+

AC or battery power rail for power circuit. (19V/12V)

ON

ON

ON

+RTCVCC

RTC Battery Power

ON

ON

ON

+1.0VALW

+1.0v Always power rail

ON

ON

ON

+1.8VALW

+1.8v Always power rail

ON

ON

ON

+3VALW

+3.3v Always power rail

ON

ON

ON

+5VALW

+5.0v Always power rail

ON

ON

ON

+1.35V

+1.35V power rail for DDR3L

ON

ON

OFF

+3V_PTP

+3.3V power rail for PTP

ON

ON

OFF

+SOC_VCC

Core voltage for SOC

ON

OFF

OFF

+SOC_VNN

GFX voltage for SOC

ON

OFF

OFF

+0.675VS

+0.675V power rail for DDR3L Terminator

ON

OFF

OFF

+1.0VS

+1.0v system power rail

ON

OFF

OFF

0
1
2
3
4
5
6
7
8
9
10
11
12
13

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0

12K +/- 5%
15K +/- 5%
20K +/- 5%
27K +/- 5%
33K +/- 5%
43K +/- 5%
56K +/- 5%
75K +/- 5%
100K +/- 5%
130K +/- 5%
160K +/- 5%
200K +/- 5%
240K +/- 5%

V AD_BID min
0 V
0.347 V
0.423 V
0.541 V
0.691 V
0.807 V
0.978 V
1.169 V
1.398 V
1.634 V
1.849 V
2.015 V
2.185 V
2.316 V

V AD_BID typ
0 V
0.354 V
0.430 V
0.550 V
0.702 V
0.819 V
0.992 V
1.185 V
1.414 V
1.650 V
1.865 V
2.031 V
2.200 V
2.329 V

V AD_BID max
0 V
0.360 V
0.438 V
0.559 V
0.713 V
0.831 V
1.006 V
1.200 V
1.430 V
1.667 V
1.881 V
2.046 V
2.215 V

2.343 V

BOARD ID Table
1

PCB Revision

Board ID
0
1
2
3
4
5
6

EVT
DVT
PVT
Pre-MP

43 level BOM table

+1.05VS

+1.05v system power rail

ON

OFF

OFF

43 Level

+1.35VS

+1.35v system power rail

ON

OFF

OFF

4319SNBOL01

+1.5VS

+1.5v system power rail

ON

OFF

OFF

4319SNBOL02

SMT MB AB211 Z5WAL UMA N2920 HDMI

SMT MB AB211 Z5WAL UMA N3520 HDMI

Description

BOM Structure

+1.8VS

+1.8v system power rail

ON

OFF

OFF

4319SNBOL03

SMT MB AB211 Z5WAL UMA N3530 HDMI

N3520@/9022@/EMC@/PCB@/1DMIC@/NTPM@
N3530@/9022@/EMC@/PCB@/1DMIC@/NTPM@

+3VS

+3.3v system power rail

ON

OFF

OFF

4319SNBOL04

SMT MB AB211 Z5WAL UMA N2930 HDMI

N2930@/9022@/EMC@/PCB@/1DMIC@/NTPM@

+5VS

+5.0v system power rail

ON

OFF

OFF

4319SNBOL05

SMT MB AB211 Z5WAL UMA N2820 HDMI

N2820@/9022@/EMC@/PCB@/1DMIC@/NTPM@

4319SNBOL06

SMT MB AB211 Z5WAL UMA N2830 HDMI

N2830@/9022@/EMC@/PCB@/1DMIC@/NTPM@

N2920@/9022@/EMC@/PCB@/1DMIC@/NTPM@

2

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

BOM Option Table

2.2K
2.2K

SOC

BH10

PCU_SMB_CLK

BG12

PCU_SMB_DATA

Item
BOM Structure
Unpop
@
Connector
CONN@
EMC requirement
EMC@

EMC requirement depop
@EMC@
KB9012
9012@
KB9022
9022@
Touch Screen I2C
TSI@
KB BL
BL@
DMIC*1
1DMIC@
DMIC*2
2DMIC@
TPM
TPM@
NTPM
NTPM@
Debug SW
DBG@

+1.8VS
BSS138
BSS138

3

2.2K
2.2K
SCL1

SDA1

77

EC_SMB_CK1

78

EC_SMB_DA1

+3VALW
100 ohm
100 ohm

7
6

BATTERY
CONN

2.2K
2.2K

KBC

SCL2

79

EC_SMB_CK2

SDA2

80

EC_SMB_DA2

3

2.2K

+3VS

2.2K
BG25

SOC_I2C2_DATA

BJ25

SOC_I2C2_CLK

2.2K

+1.8VS

2.2K

BSS138

200
202

DIMMA

SOC

SMBUS Address [A0h]

2.2K

4

BH28
BG28

200
202

DIMMB

32

WLAN

SMBUS Address [TBD]

2013/04/12

B

SOC_I2C5_CLK

4

Touch Panel

I2C5_SCL_PNL

BSS138

Compal Electronics, Inc.
2014/04/12

Deciphered Date

Title

Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

+TS_PWR

BSS138

Date:

A

2.2K
I2C5_SDA_PNL

Compal Secret Data

Security Classification
Issued Date

2.2K

+1.8VS

SOC_I2C5_DATA

SMBUS Address [A2h]

30

Touch Pad

I2C2_SCL_TP

BSS138
2.2K

KB9022

+3V_PTP

I2C2_SDA_TP

D

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

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1

1

12000mA
VR_ON

SPOK

ISL95833HRTZ-T
(PU801)

14000mA

SY8208DQNC
(PU601)

325mA

RT8207MZQW
(PU501)

5250mA

+SOC_VNN

+SOC_VCC

+1.0VALWP

SUSP

ME4856-G
(U60)

2750mA

+1.0VS

ADAPTER
SYSON

SUSP#

+1.35VP

SUSP#

TPS22966DPUR
(U59)

420mA

SUSP#

SY8003DFC_DFN8

(PU602)

958mA

SUSP#

APL5930KAI-TRG
(PU701)

1000mA

SPOK

APL5930KAI-TRG
(PU702)

110mA

2

CHARGER

B+

EC_ON

SY8208BQNC
(PU401)

+3VALWP

BATTERY

+0.675VSP

SUSP#

+1.35VS
2

TPS22966DPUR
(U11)

+1.5VSP
+1.05VSP
TPS22966DPUR
(U59)

+1.8VALWP
JP8

+3VS

+3VS_WLAN

ENVDD
LAN_PWR_EN

G5243AT11U
(U67)

+1.8VS

G5243AT11U
(U8)

+LCDVDD

+3V_LAN

3

3

EC_ON

SY8208BQNC
(PU402)

SUSP#

+5VALWP

TPS22966DPUR
(U11)

958mA

+5VS

J1

+VDDA
0 ohm

0 ohm

USB_PWR_EN#

SY6288D10CAC
(U25)

+5VS_HDD
+5VS_ODD

+USB3_VCCA

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

Power Rail

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

E

4

of

Rev
1.0
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5

4

3

DDR_A_D[0..63]

2

<13>

DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]

DDR_B_D[0..63]

<13>

DDR_B_DQS[0..7]

<13>

DDR_B_DQS#[0..7]

USOC1A
<13>

DDR_A_MA[0..15]

D

<13>

C

DDR_A_DM[0..7]

<13>
<13>
<13>

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

<13>
<13>
<13>

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

<13>

DDR_A_CS0#

<13>

DDR_A_CS2#

<13>

DDR_A_CKE0

<13>

DDR_A_CKE2

<13>

DDR_A_ODT0

<13>

DDR_A_ODT2

<13>
<13>

DDR_A_CLK0
DDR_A_CLK0#

<13>
<13>

DDR_A_CLK2
DDR_A_CLK2#

<13>

DDR_A_RST#

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

K45
H47
L41
H44
H50
G53
H49
D50
G52
E52
K48
E51
F47
J51
B49
B50

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

G36
B36
F38

B42
P51
V42
Y50
Y52
M45
M44
H51
K47
K44
D52
P44
P45
C47
D48
F44
E46
T41
P42
M50
M48
P50
P48

P41

AF44

+DDR_SOC_VREF
100K_0402_5% 1

100K_0402_5% 1

2 R960
2 R961

DDR_TERMN0
DDR_TERMN1

AF42
AH42

AD42
AB42

DDR_PWROK
DDR_CORE_PWROK

23.2_0402_1% 1
29.4_0402_1% 1
162_0402_1% 1

2 R962
2 R963
2 R964

DDR_RCOMP0
DDR_RCOMP1
DDR_RCOMP2

Follow CRB v2.0

AD44
AF45
AD45
AF40
AF41
AD40
AD41

2
1 DDR_CORE_PWROK
EMC@
C1159
0.047U_0402_25V7K

<14>
<14>
<14>

USOC1B

DRAM0_MA_0
DRAM0_MA_1
DRAM0_MA_2
DRAM0_MA_3
DRAM0_MA_4
DRAM0_MA_5
DRAM0_MA_6
DRAM0_MA_7
DRAM0_MA_8

DRAM0_MA_9
DRAM0_MA_10
DRAM0_MA_11
DRAM0_MA_12
DRAM0_MA_13
DRAM0_MA_14
DRAM0_MA_15

DRAM0_DQ_0
DRAM0_DQ_1
DRAM0_DQ_2
DRAM0_DQ_3
DRAM0_DQ_4
DRAM0_DQ_5
DRAM0_DQ_6
DRAM0_DQ_7
DRAM0_DQ_8
DRAM0_DQ_9
DRAM0_DQ_10
DRAM0_DQ_11
DRAM0_DQ_12
DRAM0_DQ_13
DRAM0_DQ_14
DRAM0_DQ_15
DRAM0_DQ_16
DRAM0_DQ_17
DRAM0_DQ_18
DRAM0_DQ_19
DRAM0_DQ_20
DRAM0_DQ_21

DRAM0_DQ_22
DRAM0_DQ_23
DRAM0_DQ_24
DRAM0_DQ_25
DRAM0_DQ_26
DRAM0_DQ_27
DRAM0_DQ_28
DRAM0_DQ_29
DRAM0_DQ_30
DRAM0_DQ_31
DRAM0_DQ_32
DRAM0_DQ_33
DRAM0_DQ_34
DRAM0_DQ_35
DRAM0_DQ_36
DRAM0_DQ_37
DRAM0_DQ_38
DRAM0_DQ_39
DRAM0_DQ_40
DRAM0_DQ_41
DRAM0_DQ_42
DRAM0_DQ_43
DRAM0_DQ_44
DRAM0_DQ_45
DRAM0_DQ_46
DRAM0_DQ_47
DRAM0_DQ_48
DRAM0_DQ_49
DRAM0_DQ_50
DRAM0_DQ_51

DRAM0_DQ_52
DRAM0_DQ_53
DRAM0_DQ_54
DRAM0_DQ_55
DRAM0_DQ_56
DRAM0_DQ_57
DRAM0_DQ_58
DRAM0_DQ_59
DRAM0_DQ_60
DRAM0_DQ_61
DRAM0_DQ_62
DRAM0_DQ_63

DRAM0_DM_0
DRAM0_DM_1
DRAM0_DM_2
DRAM0_DM_3
DRAM0_DM_4
DRAM0_DM_5
DRAM0_DM_6
DRAM0_DM_7
DRAM0_RAS#
DRAM0_CAS#
DRAM0_WE#
DRAM0_BS_0
DRAM0_BS_1
DRAM0_BS_2
DRAM0_CS_0#
DRAM0_CS_2#
DRAM0_CKE_0

RESERVED_D48
DRAM0_CKE_2
RESERVED_E46
DRAM0_ODT_0
DRAM0_ODT_2
DRAM0_CKP_0
DRAM0_CKN_0
DRAM0_CKP_2
DRAM0_CKN_2

DRAM0_DRAMRST#

0.675V

DRAM_VREF

ICLK_DRAM_TERMN_AF42
ICLK_DRAM_TERMN_AH42

DRAM0_DQSP_0
DRAM0_DQSN_0
DRAM0_DQSP_1
DRAM0_DQSN_1
DRAM0_DQSP_2
DRAM0_DQSN_2
DRAM0_DQSP_3
DRAM0_DQSN_3
DRAM0_DQSP_4
DRAM0_DQSN_4
DRAM0_DQSP_5

DRAM0_DQSN_5
DRAM0_DQSP_6
DRAM0_DQSN_6
DRAM0_DQSP_7
DRAM0_DQSN_7

B

<30>
<8>

1

DRAM_VDD_S4_PWROK
DRAM_CORE_PWROK
DRAM_RCOMP_0
DRAM_RCOMP_1
DRAM_RCOMP_2
RESERVED_AF40
RESERVED_AF41
RESERVED_AD40
RESERVED_AD41

M36
J36
P40
M40
P36
N36
K40

K42
B32
C32
C36
A37
C33
A33
C37
B38
F36
G38
F42
J42
G40
C38
G44
D42
A41
C41
A45
B46
C40
B40
B48
B47
K52
K51
T52
T51
L51

L53
R51
R53
T47
T45
Y40
V41
T48
T50
Y42
AB40
V45
V47
AD48
AD50
V48
V50
AB44
Y45
V52
W51
AC53
AC51
W53
Y51
AD52
AD51

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61

DDR_A_D62
DDR_A_D63

J38
K38
C35
B34
D40
F40
B44
C43
N53
M52
T42
T44
Y47
Y48
AB52
AA51

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4

DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

<14>

<14>

DDR_B_MA[0..15]

AY45
DDR_B_MA0
BB47
DDR_B_MA1
DDR_B_MA2 AW41
BB44
DDR_B_MA3
BB50
DDR_B_MA4
BC53
DDR_B_MA5
BB49
DDR_B_MA6
BF50
DDR_B_MA7
BC52
DDR_B_MA8

BE52
DDR_B_MA9
AY48
DDR_B_MA10
DDR_B_MA11 BE51
DDR_B_MA12 BD47
DDR_B_MA13 BA51
DDR_B_MA14 BH49
DDR_B_MA15 BH50

DDR_B_DM[0..7]

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

AV45
AV44
BB51

<14> DDR_B_RAS#
<14> DDR_B_CAS#
<14> DDR_B_WE#
<14>
<14>

<14>

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

<14>

DDR_B_CS0#

<14>

DDR_B_CS2#

<14>

DDR_B_CKE0

<14>

DDR_B_CKE2

AY47
AY44
BF52
AT44
AT45
BG47
BE46
BD44

BF48

<14>

DDR_B_ODT0

<14>

DDR_B_ODT2

AP41
AT42
AV50
AV48

<14> DDR_B_CLK0
<14> DDR_B_CLK0#

AT50
AT48

<14> DDR_B_CLK2
<14> DDR_B_CLK2#

<14>

BD38
BH36
BC36
BH42

AT51
AM42
AK50
AK52

AT41

DDR_B_RST#

DRAM1_MA_0
DRAM1_MA_1
DRAM1_MA_2
DRAM1_MA_3
DRAM1_MA_4
DRAM1_MA_5
DRAM1_MA_6
DRAM1_MA_7
DRAM1_MA_8
DRAM1_MA_9
DRAM1_MA_10
DRAM1_MA_11
DRAM1_MA_12
DRAM1_MA_13
DRAM1_MA_14
DRAM1_MA_15
DRAM1_DM_0
DRAM1_DM_1
DRAM1_DM_2
DRAM1_DM_3
DRAM1_DM_4

DRAM1_DM_5
DRAM1_DM_6
DRAM1_DM_7
DRAM1_RAS#
DRAM1_CAS#
DRAM1_WE#
DRAM1_BS_0
DRAM1_BS_1
DRAM1_BS_2
DRAM1_CS_0#
DRAM1_CS_2#
DRAM1_CKE_0
RESERVED_BE46
DRAM1_CKE_2
RESERVED_BF48
DRAM1_ODT_0
DRAM1_ODT_2
DRAM1_CKP_0
DRAM1_CKN_0

DRAM1_CKP_2
DRAM1_CKN_2

DRAM1_DRAMRST#

DRAM1_DQSP_0
DRAM1_DQSN_0
DRAM1_DQSP_1
DRAM1_DQSN_1
DRAM1_DQSP_2

DRAM1_DQSN_2
DRAM1_DQSP_3
DRAM1_DQSN_3
DRAM1_DQSP_4
DRAM1_DQSN_4
DRAM1_DQSP_5
DRAM1_DQSN_5
DRAM1_DQSP_6
DRAM1_DQSN_6
DRAM1_DQSP_7
DRAM1_DQSN_7

1 OF 13

FH8065301546401_FCBGA131170
B0@

DRAM1_DQ_0
DRAM1_DQ_1
DRAM1_DQ_2
DRAM1_DQ_3
DRAM1_DQ_4
DRAM1_DQ_5
DRAM1_DQ_6
DRAM1_DQ_7
DRAM1_DQ_8
DRAM1_DQ_9
DRAM1_DQ_10
DRAM1_DQ_11
DRAM1_DQ_12

DRAM1_DQ_13
DRAM1_DQ_14
DRAM1_DQ_15
DRAM1_DQ_16
DRAM1_DQ_17
DRAM1_DQ_18
DRAM1_DQ_19
DRAM1_DQ_20
DRAM1_DQ_21
DRAM1_DQ_22
DRAM1_DQ_23
DRAM1_DQ_24
DRAM1_DQ_25
DRAM1_DQ_26
DRAM1_DQ_27
DRAM1_DQ_28
DRAM1_DQ_29
DRAM1_DQ_30
DRAM1_DQ_31
DRAM1_DQ_32
DRAM1_DQ_33
DRAM1_DQ_34
DRAM1_DQ_35
DRAM1_DQ_36
DRAM1_DQ_37
DRAM1_DQ_38
DRAM1_DQ_39
DRAM1_DQ_40
DRAM1_DQ_41
DRAM1_DQ_42

DRAM1_DQ_43
DRAM1_DQ_44
DRAM1_DQ_45
DRAM1_DQ_46
DRAM1_DQ_47
DRAM1_DQ_48
DRAM1_DQ_49
DRAM1_DQ_50
DRAM1_DQ_51
DRAM1_DQ_52
DRAM1_DQ_53
DRAM1_DQ_54
DRAM1_DQ_55
DRAM1_DQ_56
DRAM1_DQ_57
DRAM1_DQ_58
DRAM1_DQ_59
DRAM1_DQ_60
DRAM1_DQ_61
DRAM1_DQ_62
DRAM1_DQ_63

BG38
BC40
BA42
BD42
BC38
BD36
BF42
BC44

BH32
BG32
BG36
BJ37
BG33
BJ33
BG37
BH38
AU36
AT36
AV40
AT40
BA36
AV36
AY42
AY40
BJ41
BG41
BJ45
BH46
BG40
BH40
BH48
BH47
AY52
AY51
AP52
AP51
AW51
AW53

AR51
AR53
AP47
AP45
AK40
AM41
AP48
AP50
AK42
AH40
AM45
AM47
AF48
AF50
AM48
AM50
AH44
AK45
AM52
AL51
AG53
AG51
AL53
AK51
AF52
AF51

DDR_B_D0
DDR_B_D1
DDR_B_D2

DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32

DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62

DDR_B_D63

BF40
BD40
BG35
BH34
BA38
AY38
BH44
BG43
AU53
AV52
AP42
AP44
AK47
AK48
AH52
AJ51

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5

DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

D

C

B

2 OF 13
FH8065301546401_FCBGA131170
B0@

Close To SOC Pin

+1.35V_L

+DDR_SOC_VREF
1

2
R965
4.7K_0402_1%

1

2

R966
4.7K_0402_1%

1

2

C1132
.1U_0402_16V7K

A

A

USOC1
N2830@

USOC1
N2930@

USOC1
N3530@

Issued Date
S IC FH8065301729601 SR1UX C0 2.17G ABO!
SA00007QR70

S IC FH8065301729501 SR1UW C0 1.83G ABO!
SA00007RV50

S IC FH8065301728500 SR1UV C0 2.17G ABO!
SA00007QQ50

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

VLV-M SOC Memory DDR3L

3

2

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

1

5

of

Rev
1.0
39


5

4

3

2

1

D

D

USOC1C

C26
C28
B28
C27
B26

1 R968
2 DDI0_RCOMPP
402_0402_1% DDI0_RCOMPN

Follow CRB v2.0 0ohm till to GND

C

AK12
AK13
AM14
AM13
AM3
AM2

DDI1_AUXP
DDI1_AUXN

DDI0_HPD

1.8V

1.8V

DDI1_HPD

DDI0_DDCDATA
DDI0_DDCCLK

1.8V
1.8V

1.8V
1.8V

DDI1_DDCDATA
DDI1_DDCCLK

1.8V
1.8V
1.8V

DDI1_VDDEN
DDI1_BKLTEN
DDI1_BKLTCTL

DDI0_VDDEN
DDI0_BKLTEN

DDI0_BKLTCTL

VSS_AH3
VSS_AH2

DDI0_RCOMP_P
DDI0_RCOMP_N
RESERVED_AM14
RESERVED_AM13
VSS_AM3
VSS_AM2

RESERVED_AH14
RESERVED_AH13
RESERVED_AF14
RESERVED_AF13
VGA_RED
VGA_BLUE
VGA_GREEN
VGA_IREF
VGA_IRTN

1

+1.8VS

@
R970
10K_0402_5%

1

2

B

@

T186

GPIO_NC12

RESERVED_T2
RESERVED_T3
RESERVED_AB3
RESERVED_AB2
RESERVED_Y3
RESERVED_Y2
RESERVED_W3
RESERVED_W1
RESERVED_V2
RESERVED_V3
RESERVED_R3
RESERVED_R1
RESERVED_AD6
RESERVED_AD4
RESERVED_AB9
RESERVED_AB7
RESERVED_Y4
RESERVED_Y6

RESERVED_V4
RESERVED_V6
GPIO_S0_NC_13
GPIO_S0_NC14
RESERVED_AB14
GPIO_S0_NC_12
RESERVED_C30

VGA_HSYNC
VGA_VSYNC

3.3V
3.3V

VGA_DDCCLK
VGA_DDCDATA

RESERVED_T7
RESERVED_T9
RESERVED_AB13
RESERVED_AB12
RESERVED_Y12
RESERVED_Y13
RESERVED_V10
RESERVED_V9
RESERVED_T12
RESERVED_T10
RESERVED_V14
RESERVED_V13
RESERVED_T14

RESERVED_T13
RESERVED_T6
RESERVED_T4
RESERVED_P14
GPIO_S0_NC_15
GPIO_S0_NC_16
GPIO_S0_NC_17
GPIO_S0_NC_18
GPIO_S0_NC_19
GPIO_S0_NC_20
GPIO_S0_NC_21
GPIO_S0_NC_22
GPIO_S0_NC_23
GPIO_S0_NC_24
GPIO_S0_NC_25
GPIO_S0_NC_26

2

@
T187
R971
10K_0402_5%

GPIO_NC13
GPIO_NC14

T2
T3
AB3

AB2
Y3
Y2
W3
W1
V2
V3
R3
R1
AD6
AD4
AB9
AB7
Y4
Y6
V4
V6
A29
C29
AB14
B30
C30

3.3V
3.3V

Follow CRB v2.0

3 OF 10

AG3
AG1
AF3
AF2
AD3
AD2
AC3
AC1

EDP_TXP0 <15>
EDP_TXN0 <15>
EDP_TXP1 <15>
EDP_TXN1 <15>

eDP Panel

AK3
AK2
K30
P30 DDI1_ENABLE R967 1
G30

EDP_AUXP
EDP_AUXN

<15>
<15>

EDP_HPD#

<15>

2 2.2K_0402_5% +1.8VS

N30 DDI1_ENVDD
J30 DDI1_ENBKL
M30 DDI1_PWM
AH3
AH2

Follow CRB v2.0 0ohm till to GND

AH14
AH13
AF14
AF13
BA3
AY2
BA1
AW1
AY3

C

CRT_R
CRT_B
CRT_G
CRT_IREF 1
R969

CRT_R
CRT_B
CRT_G

2
357_0402_1%

BD2 CRT_HSYNC
BF2 CRT_VSYNC

CRT_HSYNC
CRT_VSYNC

BC1 CRT_DDC_CLK
BC2 CRT_DDC_DATA
T7
T9
AB13
AB12
Y12
Y13
V10
V9
T12
T10
V14
V13
T14
T13
T6

T4
P14
F34
M32
D28
J28
K34
D34
F32
F28
K28
J34
N32
D32

<17>
<17>

CRT

CRT_DDC_CLK <17>
CRT_DDC_DATA <17>

CRT
8
7
6
5

CRT_R

CRT_G
CRT_B

RP43
150_0804_8P4R_1%
1
2
3
4

+1.8VS

eDP

B

1
DDI1_ENBKL

U61

NC

4

Y

2

A

ENBKL

<22>
+3VS

NL17SZ07DFT2G_SC70-5
SA00004BV00
9012@

R1142 1

1 9012@ 2
ENBKL
4.7K_0402_5%
R1159

RS@ 2 0_0402_5%

+1.8VS

FH8065301546401_FCBGA131170
B0@

5

GPIO_S0_NC[13]:
Multiplexed with Hardware

<17>

<17>
<17>

5

HDMI_DDCDATA
HDMI_DDCCLK

1.0V
1.0V

DDI0_AUXP
DDI0_AUXN

DDI1_TXP_0
DDI1_TXN_0
DDI1_TXP_1
DDI1_TXN_1
DDI1_TXP_2
DDI1_TXN_2
DDI1_TXP_3
DDI1_TXN_3

P

HDMI_HPD#

<16>
<16>

1.0V

G

D27

<16>

1.0V

3

AL3
AL1

DDI0_TXP_0
DDI0_TXN_0
DDI0_TXP_1
DDI0_TXN_1
DDI0_TXP_2
DDI0_TXN_2
DDI0_TXP_3
DDI0_TXN_3

Straps Pin:MDSI_DDCDATA

1

Y
A

4

ENVDD

<15>

RP45

5

2013/04/12

4

INVT_PWM_SOC

A

NL17SZ07DFT2G_SC70-5
SA00004BV00

Compal Electronics, Inc.
2014/04/12

Deciphered Date

Title

Date:

4

3

1
2
3
4
100K_0804_8P4R_5%

<15>

VLV-M SOC Display

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

8
7
6
5

P
Y

A

Compal Secret Data

Security Classification
Issued Date

U64

NC

3

2

DDI1_ENBKL
DDI1_ENVDD
DDI1_PWM

G

1
DDI1_PWM

2

NL17SZ07DFT2G_SC70-5
SA00004BV00

+1.8VS

A

2

INVT_PWM_SOC 1
4.7K_0402_5%
R1161
U62

NC

3

DDI1_ENVDD 2

1
ENVDD
4.7K_0402_5%
R1160

P

HDMI

AV3
AV2
AT2
AT3
AR3

AR1
AP3
AP2

HDMI_TX2+
HDMI_TX2HDMI_TX1+
HDMI_TX1HDMI_TX0+
HDMI_TX0HDMI_CLK+
HDMI_CLK-

G

<16>
<16>
<16>
<16>
<16>
<16>
<16>
<16>

2

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

1

6

of

Rev
1.0
39


5

4

3

2

1

D

D

USOC1D

HDD

ODD

<20>

<20>

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

<20>
<20>

SATA_PRX_DTX_P0
SATA_PRX_DTX_N0

<20>
<20>

SATA_PTX_DRX_P1
SATA_PTX_DRX_N1

<20>
<20>

SATA_PRX_DTX_P1
SATA_PRX_DTX_N1

BF6
BG7
AU16
AV16
BD10
BF10
AY16

BA16

Follow CRB V2.0 0ohm till to GND
<8>

SOC_SCI#
@ T188

C

SOC_SCI#
DEVSLP_SOC

1 R972
2 SATA_RCOMPP
402_0402_1% SATA_RCOMPN

BB10
BC10
BA12
AY14
AY12
AU18
AT18
AT22
AV20
AU22
AV22
AT20
AY24

AU26
AT26
AU20
AV26
BA24
AY18
BA18
AY20
BD20
BA20
BD18
BC18

AY26
AT28
BD26
AU28
BA26
BC24
AV28
BF22
BD22

B

BF26

SATA_TXP_0
SATA_TXN_0

PCIE_TXP_0
PCIE_TXN_0

SATA_RXP_0
SATA_RXN_0

PCIE_RXP_0
PCIE_RXN_0

SATA_TXP_1
SATA_TXN_1

PCIE_TXP_1
PCIE_TXN_1

SATA_RXP_1
SATA_RXN_1

PCIE_RXP_1
PCIE_RXN_1

VSS_BB10
VSS_BC10

PCIE_TXP_2
PCIE_TXN_2

SATA_GP0 / GPIO_S0_SC_0
SATA_GP1 / SATA_DEVSLP_0 / GPIO_S0_SC_1
SATA_LED# / GPIO_S0_SC_2

PCIE_RXP_2
PCIE_RXN_2
PCIE_TXP_3
PCIE_TXN_3

SATA_RCOMP_P
SATA_RCOMP_N

PCIE_RXP_3
PCIE_RXN_3
MMC1_CLK / GPIO_S0_SC_16
VSS_BB7
VSS_BB5

MMC1_D0 / GPIO_S0_SC_17
MMC1_D1 / GPIO_S0_SC_18
MMC1_D2 / GPIO_S0_SC_19
MMC1_D3 / GPIO_S0_SC_20
MMC1_D4 / GPIO_S0_SC_21
MMC1_D5 / GPIO_S0_SC_22
MMC1_D6 / GPIO_S0_SC_23
MMC1_D7 / GPIO_S0_SC_24

PCIE_CLKREQ_0# / GPIO_S0_SC_3
PCIE_CLKREQ_1# / GPIO_S0_SC_4
PCIE_CLKREQ_2# / GPIO_S0_SC_5
PCIE_CLKREQ_3# / GPIO_S0_SC_6
SD3_WP / GPIO_S0_SC_7

MMC1_CMD / GPIO_S0_SC_25
MMC1_RST# / SATA_DEVSLP_0 / GPIO_S0_SC_26

PCIE_RCOMP_P
PCIE_RCOMP_N
RESERVED_BB4
RESERVED_BB3

MMC1_RCOMP
SD2_CLK / GPIO_S0_SC_27
SD2_D0 / GPIO_S0_SC_28
SD2_D1 / GPIO_S0_SC_29
SD2_D2 / GPIO_S0_SC_30
SD2_D3_CD# / GPIO_S0_SC_31
SD2_CMD / GPIO_S0_SC_32

RESERVED_AV10
RESERVED_AV9

HDA_LPE_RCOMP
HDA_RST# / LPE_I2S0_CLK / GPIO_S0_SC_8
HDA_SYNC / LPE_I2S0_FRM / GPIO_S0_SC_9
HDA_CLK / LPE_I2S0_DATAOUT / GPIO_S0_SC_10
HDA_SDO / LPE_I2S0_DATAIN / GPIO_S0_SC_11
HDA_SDI0 / LPE_I2S1_CLK / GPIO_S0_SC_12
HDA_SDI1 / LPE_I2S1_FRM / GPIO_S0_SC_13
SD3_CLK / GPIO_S0_SC_33 HDA_DOCKRST# / LPE_I2S1_DATAOUT / GPIO_S0_SC_14
SD3_D0 / GPIO_S0_SC_34
HDA_DOCKEN# / LPE_I2S1_DATAIN / GPIO_S0_SC_15
SD3_D1 / GPIO_S0_SC_35

SD3_D2 / GPIO_S0_SC_36
LPE_I2S2_CLK / SATA_DEVSLP_1 / GPIO_S0_SC_62
SD3_D3 / GPIO_S0_SC_37
LPE_I2S2_FRM / GPIO_S0_SC_63
SD3_CD# / GPIO_S0_SC_38
LPE_I2S2_DATAIN / GPIO_S0_SC_64
SD3_CMD / GPIO_S0_SC_39
LPE_I2S2_DATAOUT / GPIO_S0_SC_65
SD3_1P8EN / GPIO_S0_SC_40
SD3_PWREN# / GPIO_S0_SC_41
RESERVED_P34
RESERVED_N34
SD3_RCOMP
RESERVED_AK9
RESERVED_AK7
4 OF 10

PROCHOT#

AY7 PCIE_PTX_DRX_P0
AY6 PCIE_PTX_DRX_N0

.1U_0402_16V7K 1
.1U_0402_16V7K 1

2 C1133
2 C1134

AT14 PCIE_PRX_DTX_P0
AT13 PCIE_PRX_DTX_N0

PCIE_PTX_C_DRX_P0
PCIE_PTX_C_DRX_N0
PCIE_PRX_DTX_P0
PCIE_PRX_DTX_N0

AV6 PCIE_PTX_DRX_P1
AV4 PCIE_PTX_DRX_N1

.1U_0402_16V7K 1
.1U_0402_16V7K 1

2 C1135
2 C1000

AT10 PCIE_PRX_DTX_P1
AT9 PCIE_PRX_DTX_N1

PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1
PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1

<18>
<18>

PCIE LAN

<18>
<18>

<19>
<19>

WLAN

<19>
<19>

AT7
AT6
AP12
AP10
AP6
AP4

C

+1.8VS

AP9
AP7

RP51

BB7
BB5
BG3
BD7
BG5
BE3

BD5

LAN_CLKREQ#
WLAN_CLKREQ#
PCIE_CLKREQ_2#
PCIE_CLKREQ_3#

AP14
AP13

PCIE_RCOMPP
PCIE_RCOMPN

1
2
3
4

LAN_CLKREQ#
WLAN_CLKREQ#
PCIE_CLKREQ_2#
PCIE_CLKREQ_3#

Follow CRB V2.0 0ohm till to GND
LAN_CLKREQ# <18>
WLAN_CLKREQ# <19>

8
7
6

5
10K_0804_8P4R_5%
RP46

8
7
6
5

HDA_SYNC
HDA_SDOUT
HDA_BIT_CLK
HDA_RST#

1 R975
2
402_0402_1%

BB4
BB3

1
2
3
4

HDA_SYNC_AUDIO
<24>
HDA_SDOUT_AUDIO <24>
HDA_BITCLK_AUDIO <24>

HDA_RST_AUDIO# <24>

33_0804_8P4R_5%
EMC@

AV10
AV9
HDA_RCOMP
BF20
BG22
BH20
BJ21
BG20
BG19
BG21
BH18
BG18
BF28
BA30
BD28
BC30

HDA_RCOMP
HDA_RST#
HDA_SYNC
HDA_BIT_CLK
HDA_SDOUT
HDA_SDIN0

2

1

49.9_0402_1%

2 22P_0402_50V8J

@EMC@

@
T189
@
T190
@
T191

HDA_SDIN0

<24>

Follow CRB v2.0

GPIO_S0_SC_65

P34
N34

R979
73.2_0402_1%
1
2

AK9
AK7
C24

2

1

+1.8VS

GPIO_S0_SC_63 R977 2

1 10K_0402_5%

+1.0VS
H_PROCHOT#

Internal PD 2K

B

GPIO_S0_SC_63:
BIOS Boot Selection
0 = LPC
1 = SPI

GPIO_S0_SC_63

FH8065301546401_FCBGA131170

B0@

R976 1

HDA_BITCLK_AUDIOC1001

<22>

GPIO_S0_SC_65:
Security Flash Descriptors
0 = Override
1 = Normal Operation   (Internal PU)

@EMC@
C1002
10P_0402_50V8J

1

+1.8VS

2

R978
10K_0402_5%
GPIO_S0_SC_65

EC programing :
"High"for Flash BIOS

1

D
A

3

S

Issued Date

2013/04/12

2014/04/12

Deciphered Date

Title

VLV-M SOC SATA/PCI-E/HDA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

A

<22>

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2
TXE_DBG
G
Q62
MESS138W-G_SOT323-3

2

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

1

7

of

Rev
1.0
39


5

4

3

2

1

+3VS

3
GND

GND

2

4

3

XTAL_25M_OUT

2

R984 1
R985 1

ICLK_ICOMP
ICLK_RCOMP

AD10
AD12

C1004
10P_0402_50V8J

2 4.02K_0402_1% ICLK_ICOMP
2 47.5_0402_1% ICLK_RCOMP

RESERVED_AD9

AD14
AD13

ICLK_ICOMP
ICLK_RCOMP

LAN

<18>
<18>

CLK_PCIE_LAN#
CLK_PCIE_LAN

WLAN

<19>
<19>

CLK_PCIE_WLAN#
CLK_PCIE_WLAN

PCIE_CLKN_0
PCIE_CLKP_0

AF9
AF7

PCIE_CLKN_2
PCIE_CLKP_2

AM4
AM6

R989 1
R1026 1

R1024 1

5
6
7
8

XDP_H_TDI
XDP_H_TMS
XDP_H_TCK
XDP_H_TRST#
XDP_H_TCK
XDP_H_TRST#
XDP_H_TMS
XDP_H_TDI
XDP_H_TDO
XDP_H_PRDY#
XDP_H_PREQ_BUF#

51_0804_8P4R_5%
C

@ T193
@T193
SOC_SPI_MISO
SOC_SPI_MOSI
SOC_SPI_CLK

<15> TS_INT_R#
<23> TP_INT#

D14
G12
F14
F12
G16
D18
F16
AT34

SOC_LID_OUT#
SOC_SMI#

PMC_ACIN

D40

1

2

2.2K_0402_5%

+1.8VALW

1 RB751V40_SC76-2

ACIN

D26

G24
F18
F22
D22
J20
D20
F26
K26
J26
BG9
F20
J24
G18

SVID_ALERT#
SVID_DATA
SVID_CLK
SIO_PWM_0 / GPIO_S0_SC_94
SIO_PWM_1 / GPIO_S0_SC_95

GPIO_S5_22
GPIO_S5_23
GPIO_S5_24
GPIO_S5_25
GPIO_S5_26
GPIO_S5_27
GPIO_S5_28
GPIO_S5_29
GPIO_S5_30

GPIO_S5_8
GPIO_S5_9
GPIO_S5_10

<18,19,22,23>

P

NL17SZ07DFT2G_SC70-5
SA00004BV00

PLT_RST# Buffer

D

+1.8VALW
T192@ 32.768k

PMC_SUSCLK
PMC_SLP_S4#
PMC_SLP_S3#
GPIO_S5_14
PMC_ACIN
PMC_PCIE_WAKE#
PMC_BATLOW#
PMC_PWRBTN#
PMC_RSTBTN#
PMC_PLTRST#
GPIO_S5_17
PMC_SUS_STAT#

output

RP47
1
2
3
4

PMC_PCIE_WAKE#
PMC_BATLOW#
GPIO_S5_14
LS_OE

T209@

PMC_CORE_PWROK EMC@

C1007 1

2 0.047U_0402_25V7K

DDR_CORE_PWROK EMC@

C1158 1

2 0.01U_0402_16V7K

C1006 1

2 .1U_0402_16V7K

T205@
T207@

C11 RTC_TEST#
C12 RTC_RST#
B10
B7

EC_RSMRST#
PMC_CORE_PWROK

C9
A9
B8
P22

ILB_RTC_X1
ILB_RTC_X2
ILB_RTC_EXTPAD

8
7
6
5
10K_0804_8P4R_5%

PMC_PLTRST#

EC_RSMRST#

EMC@

R990 1

<22>

2 100K_0402_5%

C1155 1

EMC@

1
2
C1008
.1U_0402_16V7K

+RTCVCC

B24 VR_SVID_ALERT#_SOC R1065 1
A25 VR_SVID_DATA_SOC
R1066 1
C25

2 .1U_0402_16V7K

RP55
1

PMC_SLP_S4# 2
SOC_KBRST# 3
SOC_LID_OUT#4

R1064
73.2_0402_1%
2 20_0402_1%
2 16.9_0402_1%

VR_SVID_ALERT# <33>
VR_SVID_DATA <33>
VR_SVID_CLK <33>

K24
N24
M20
J18
M18
K18
K20
M22
M24

SIO_SPI_CS# / GPIO_S0_SC_66
SIO_SPI_MISO / GPIO_S0_SC_67
SIO_SPI_MOSI / GPIO_S0_SC_68
SIO_SPI_CLK / GPIO_S0_SC_69

8
7

6
5

0_0804_8P4R_5%
9022@
+3VALW_EC
9012@
19
VCCA
VCCB

+1.8VALW
1
2
R994
10M_0402_5%

C

EC_SLP_S4#
EC_KBRST#
EC_LID_OUT#

0_0804_8P4R_5%
9022@
RP56
8
7 EC_SMI#
6 EC_SCI#
5 PBTN_OUT#

1
2
SOC_SMI#
3
SOC_SCI#
PMC_PWRBTN# 4

AU32
AT32

U54
2
PMC_SLP_S3#
PMC_SLP_S4#
SOC_KBRST#
SOC_LID_OUT#
SOC_SERIRQ
SOC_SMI#
SOC_SCI#
PMC_PWRBTN#

32.768KHZ_12.5PF_Q13FC135000040
2
Y8 1
1

2

5 OF 13

3.3V

PLT_RST_BUF#

1
2
C1174
@EMC@
0.01U_0402_16V7K

PLT_RST_BUF#

ILB_RTC_X1
ILB_RTC_X2

GPIO_RCOMP

A

<22,28>

BF34
BD34
BD32
BF32

4

Y

PMC_PLTRST# 2

2

R983 2

+1.0VS

RTC domain
ILB_RTC_X1
ILB_RTC_X2
ILB_RTC_EXTPAD
RTC_VCC_P22

2

B

PMC_RSMRST#
PMC_CORE_PWROK

GPIO_S5_0
GPIO_S5_1 / PMC_WAKE_PCIE_1
GPIO_S5_2 / PMC_WAKE_PCIE_2
GPIO_S5_3 / PMC_WAKE_PCIE_3
GPIO_S5_4
GPIO_S5_5 / PMU_SUSCLK_1
GPIO_S5_6 / PMU_SUSCLK_2
GPIO_S5_7 / PMU_SUSCLK_3

N26

AU34
AV34
BA34
AY34

EC_RSMRST#

PCU_SPI_CS_0#
PCU_SPI_CS_1# / GPIO_S5_21
PCU_SPI_MISO
PCU_SPI_MOSI
PCU_SPI_CLK

C13
A13
C19
GPIO_RCOMP

ILB_RTC_TEST#
ILB_RTC_RST#

TAP_TCK
TAP_TRST#
TAP_TMS
TAP_TDI
TAP_TDO
TAP_PRDY#

TAP_PREQ#
RESERVED_AT34

B18
B16
C18
A17
C17
C16
B14
C15

SOC_KBRST#
TS_INT#_CPU
TP_INT#_CPU

2 R1016
2 R1015

PMC_PLT_CLK_0 / GPIO_S0_SC_96
PMC_PLT_CLK_1 / GPIO_S0_SC_97
PMC_PLT_CLK_2 / GPIO_S0_SC_98
PMC_PLT_CLK_3 / GPIO_S0_SC_99
PMC_PLT_CLK_4 / GPIO_S0_SC_100
PMC_PLT_CLK_5 / GPIO_S0_SC_101

C23
C21
B22
A21

C22

SOC_SPI_CS0#

0_0402_5%1 TSI@
0_0402_5%1 RS@

RESERVED_AM9
RESERVED_AM10

BH7
BH5
BH4
BH8
BH6
BJ9

RP52
4
3
2
1

PCIE_CLKN_3
PCIE_CLKP_3

AM9
AM10

2 51_0402_5% XDP_H_PRDY#

2 51_0402_5% XDP_H_TDO
2 200_0402_5% XDP_H_PREQ_BUF#

PMC_SUSPWRDNACK / GPIO_S5_11
PMC_SUSCLK_0 / GPIO_S5_12
PMC_SLP_S0IX# / GPIO_S5_13
PMC_SLP_S4#
PMC_SLP_S3#
GPIO_S5_14
PMC_ACPRESENT
PMC_WAKE_PCIE_0# / GPIO_S5_15
PMC_BATLOW#
PMC_PWRBTN# / GPIO_S5_16
PMC_RSTBTN#
PMC_PLTRST#
GPIO_S5_17
PMC_SUS_STAT# / GPIO_S5_18

PCIE_CLKN_1
PCIE_CLKP_1

AK4
AK6

+1.8VALW

SIO_UART2_RXD / GPIO_S0_SC_74
SIO_UART2_TXD / GPIO_S0_SC_75
SIO_UART2_RTS# / GPIO_S0_SC_76
SIO_UART2_CTS# / GPIO_S0_SC_77

RESERVED_AD10
RESERVED_AD12

AF6
AF4

For XDP use

SIO_UART1_RXD / GPIO_S0_SC_70
SIO_UART1_TXD / GPIO_S0_SC_71
SIO_UART1_RTS# / GPIO_S0_SC_72
SIO_UART1_CTS# / GPIO_S0_SC_73

R982
4.7K_0402_5%

U53

NC

3

AD9

1

2

ICLK_OSCIN

ICLK_OSCOUT

1

1

1

2

C1003
10P_0402_50V8J

D

1
1

AH12
AH10

XTAL_25M_IN
XTAL_25M_OUT

R981
1M_0402_5%

Y7
25MHZ_10PF_7V25000014

1.8V

2

1

USOC1E

G

XTAL_25M_IN

5

1

+1.8VS

1
C1009
18P_0402_50V8J

2

<9>
C1010
18P_0402_50V8J

SOC_SERIRQ

<7>

SOC_SCI#

AV32
BA28
AY28
AY30

1
3
4
5
6
7
8
9
10

LS_OE

A1
A2
A3
A4
A5
A6
A7
A8

B1
B2
B3
B4
B5
B6
B7
B8

OE

GND

20
18
17
16
15
14
13
12

EC_SLP_S3# <22>
EC_SLP_S4# <22>
EC_KBRST# <22>
EC_LID_OUT# <22>
EC_SERIRQ <22,23>
EC_SMI# <22>
EC_SCI# <22>
PBTN_OUT# <22>

11

TXB0108PWR_TSSOP20
B

R995
49.9_0402_1%

SOC_SERIRQ

R1021 2 NTPM@ 1 0_0402_5%

EC_SERIRQ

PMC_SLP_S3#

R1025 2 NTPM@ 1 0_0402_5%

EC_SLP_S3#

1

FH8065301546401_FCBGA131170
B0@

+1.8VALW

+3VALW_EC
U71

SOC_SERIRQ

1
2
3

+1.8VALW

EC_SERIRQ

C1013

2

1 .1U_0402_16V7K

RTC_TEST#

PMC_SLP_S3#

1
2
3
4

8
7
6
5

SPI_CS0#
SPI_MISO
SPI_MOSI
SPI_CLK

1

2

SPI_CS0#
SPI_MISO
SPI_WP#

1
2
3
4

CS#
VCC
DO(IO1) HOLD#(IO3)
WP#(IO2)
CLK
GND
DI(IO0)

8
7
6

5

4
3
2
1

5
6
7
8

SPI_CS0#
SPI_MISO
SPI_MOSI
SPI_CLK

22_0804_8P4R_5%
EMC@

+CHGRTC
D22
2
1

SPI_HOLD#
SPI_CLK
SPI_MOSI

W25Q64DWSSIG_SO8

RP48
SOC_SPI_CS0#
SOC_SPI_MISO
SOC_SPI_MOSI
SOC_SPI_CLK

+RTCBATT

C1012
1U_0402_6.3V6K

U56

22_0804_8P4R_5%
EMC@

A

C1011
1U_0402_6.3V6K

W=20mils
2 RS@
1
RTC_TEST#
0_0402_5%
R1088
2
1

RTC_RST#
@
0_0402_5%
R1089

Clear CMOS
Close to RAM door

CLR_CMOS#
@
JCMOS1
SHORT PADS

CLR_CMOS#

<22>

3
1

2

C151
.1U_0402_16V7K

3.3V
<22>

PMC_CORE_PWROK

2
1
@EMC@ C1014
10P_0402_50V8J

Issued Date

2013/04/12

2014/04/12

Deciphered Date

Title

4

2

NC

Y
A

R993
10K_0402_5%

U55

1.35V

4

DDR_CORE_PWROK

3

<5>

NL17SZ07DFT2G_SC70-5
SA00004BV00

VLV-M SOC CLK/PMU/SPI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

1

Compal Electronics, Inc.

Compal Secret Data

Security Classification
1
2
@EMC@ R1002
33_0402_5%

2

+1.35VS
+3VALW

Reserve for EMI(Near SPI ROM)
SPI_CLK

EC_SLP_S3#

W=20mils
+RTCVCC

W=10mil

BAS40-04_SOT23-3

1

1

EC_SPICS#
EC_MISO

EC_MOSI
EC_SPICLK

+BIOS_SPI

2

RP53

3

TPM@ Q83
MESS138W-G_SOT323-3

5

From EC
(For share ROM)

1
20K_0402_1%

P

2
1 R997

G

2

RTC_RST#

3

SPI_HOLD#

1

2 3.3K_0402_5%

D

R1000 1

R1034
10K_0402_5%
TPM@

R996
20K_0402_1%
2
1

S

SPI_WP#

1 0_0402_5%

G

2 3.3K_0402_5%

+RTCVCC

RS@
2

R998
R1001 1

2

+1.8VALW

SPI_CS0#

2

2 3.3K_0402_5%

1

+BIOS_SPI
R999 1

From CPU

6

5
4

VCCB
EO
B4

G2129TL1U_SC70-6

+BIOS_SPI

<22> EC_SPICS#
<22> EC_MISO
<22> EC_MOSI
<22> EC_SPICLK

+1.8VALW

TPM@

VCCA
GND
A4

2

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

1

8

of

Rev
1.0
39

A


5

4

3

2

1

USOC1F

M3
L1
K2
K3

M2
N3
P2
L3

J3
P3
H3
B12

USB3.0 Port

<21>
<21>

USB20_P0
USB20_N0

USB Hub

<21>
<21>

USB20_P1
USB20_N1

Touch Panel

<15>
<15>

USB20_P2
USB20_N2

Camera

+1.8VALW
R1007 1
R1009 1

2 10K_0402_5% USB_OC0#
2 10K_0402_5% USB_OC1#

<15>
<15>

M16
K16
J14
G14
K12
J12
K10
H10

USB20_P3
USB20_N3

1K_0402_1%
1K_0402_1%

1
1

2 R1004 ICLK_USB_TERMP
2 R1005 ICLK_USB_TERMN

D10
F10

C

USB_OC0#

USB_OC1#

C20
B20

RESERVED_M10
RESERVED_M9

GPIO_S5_32
GPIO_S5_33
GPIO_S5_34
GPIO_S5_35
GPIO_S5_36
GPIO_S5_37
GPIO_S5_38
GPIO_S5_39

RESERVED_P6
RESERVED_P7
RESERVED_M7
USB3_REXT0
RESERVED_P10
RESERVED_P12
RESERVED_M4
RESERVED_M6

GPIO_S5_40
GPIO_S5_41
GPIO_S5_42
GPIO_S5_43

USB3_RXP0
USB3_RXN0
USB3_TXP0
USB3_TXN0

USB_DP0
USB_DN0

M10
M9
D

P6
P7
R1003

M7
1.24K_0402_1%
M12 USB3_REXT0 1
2
P10
P12
M4
M6
D4
E3

PCH_USB3_RX0_P
PCH_USB3_RX0_N

K6
K7

PCH_USB3_TX0_P
PCH_USB3_TX0_N

<21>
<21>

USB3 Port 0

<21>
<21>

USB_DP1
USB_DN1

BIOS/EFI Top Swap

USB_DP2
USB_DN2
USB_DP3
USB_DN3

RESERVED_H8
RESERVED_H7

+1.8VS

H8
H7

ICLK_USB_TERMP
ICLK_USB_TERMN

RESERVED_H4
RESERVED_H5

H4
H5

USB_OC_0# / GPIO_S5_19
USB_OC_1# / GPIO_S5_20

GPIO_S0_SC_56

USB_PLL_MON

M13

B4
B5
E2
D2

NOTE: Ref checklist rev1.2 p.25
USB_HSIC_RCOMP must NOT float if they are not being used.
1
R1012
49.9_0402_1%1

+1.8VS
RP49
5
6
7
8

B

2
HSIC_RCOMP
45.3_0402_1%

4
3

2
1

PCU_SMB_CLK
PCU_SMB_DATA
PCU_SMB_ALERT#

4.7K_0804_8P4R_5%
+1.8VS

<22,23>
<22,23>
<22,23>
<22,23>
<22,23>
<22>
<23>
<23>
<8>

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_CLK_EC
LPC_CLK_TPM
LPC_CLKRUN#
SOC_SERIRQ

2 R1013 LPC_RCOMP

22_0402_5% 1 EMC@ 2 R1014 LPC_CLK_0
22_0402_5% 1 TPM@ 2 R1017 LPC_CLK_1

A7

BF18
BH16
BJ17
BJ13
BG14
BG17
BG15
BH14
BG16
BG13

USB_RCOMPO
USB_RCOMPI

GPIO_S0_SC_55
GPIO_S0_SC_56
GPIO_S0_SC_57 / PCU_UART_TXD
GPIO_S0_SC_58
GPIO_S0_SC_59
GPIO_S0_SC_60
GPIO_S0_SC_61 / PCU_UART_RXD

USB_PLL_MON

USB_HSIC0_DATA
USB_HSIC0_STROBE

ILB_8254_SPKR / GPIO_S0_SC_54

USB_HSIC1_DATA
USB_HSIC1_STROBE
SIO_I2C0_DATA / GPIO_S0_SC_78
SIO_I2C0_CLK / GPIO_S0_SC_79

BD12
BC12
BD14
BC14
BF14
BD16
BC16
BH12

GPIO_S0_SC_56
DBG_UART_TXD

T203@

DBG_UART_RXD

T204@

SOC_SPKR

SOC_SPKR

GPIO_S0_SC_56: Top Swap( A16 Override )
0 = Top address bit is unchanged
1 = Top address bit is inverted
Reference EDS2.0 Page 51

<24>

BH22
BG23

USB_HSIC_RCOMP
SIO_I2C1_DATA / GPIO_S0_SC_80
SIO_I2C1_CLK / GPIO_S0_SC_81
LPC_RCOMP / VGA_RCOMP
ILB_LPC_AD_0 / GPIO_S0_SC_42
ILB_LPC_AD_1 / GPIO_S0_SC_43
ILB_LPC_AD_2 / GPIO_S0_SC_44
ILB_LPC_AD_3 / GPIO_S0_SC_45
ILB_LPC_FRAME# / GPIO_S0_SC_46
ILB_LPC_CLK_0 / GPIO_S0_SC_47
ILB_LPC_CLK_1 / GPIO_S0_SC_48
ILB_LPC_CLKRUN# / GPIO_S0_SC_49
ILB_LPC_SERIRQ / GPIO_S0_SC_50

For Touch Screen

BG24

BH24

+1.8VS
SOC_I2C5_DATA R1143 1

SIO_I2C2_DATA / GPIO_S0_SC_82
SIO_I2C2_CLK / GPIO_S0_SC_83

@
R1011
10K_0402_5%

BG25
BJ25

SOC_I2C2_DATA
SOC_I2C2_CLK

SOC_I2C5_CLK

TSI@ 2 2.2K_0402_5%

R1144 1

TSI@ 2 2.2K_0402_5%
+1.8VS

SIO_I2C3_DATA / GPIO_S0_SC_84
SIO_I2C3_CLK / GPIO_S0_SC_85

B

BG26
BH26
5

2

D6
C7

C

BF27
BG27

TSI@
3
SOC_I2C5_DATA 4
Q80A
DMN63D8LDW_SOT363-6

I2C5_SDA_PNL

<15>

I2C5_SCL_PNL

<15>

BG12
PCU_SMB_DATA
BH10
PCU_SMB_CLK
PCU_SMB_ALERT# BG11

2

S

4 PCU_SMB_CLK
Q79A
DMN63D8LDW_SOT363-6

PCU_SMB_DATA / GPIO_S0_SC_51
PCU_SMB_CLK / GPIO_S0_SC_52
PCU_SMB_ALERT# / GPIO_S0_SC_53

SIO_I2C6_DATA / GPIO_S0_SC_90
SIO_I2C6_CLK / GPIO_S0_SC_91 / SD3_WP

G

6

1

PCU_SMB_DATA

S

EC_SMB_DA2

D

<13,14,19,22>

Q79B
DMN63D8LDW_SOT363-6

SIO_I2C5_DATA / GPIO_S0_SC_88
SIO_I2C5_CLK / GPIO_S0_SC_89

ILB_LPC_CLK_0 : Output
Need Check with EC

of

25MHz,
6 OF 13

ILB_LPC_CLK_1 is for CLK_0 feedback.(Input)
Set to Output for Normal Usage

GPIO_S0_SC_092
GPIO_S0_SC_093

SOC_I2C5_DATA
SOC_I2C5_CLK

G

BH28
BG28

TSI@
6

1
Q80B
DMN63D8LDW_SOT363-6

SOC_I2C5_CLK

D

3

EC_SMB_CK2

D

<13,14,19,22>

G

Pull High at EC side

S

5

2

SIO_I2C4_DATA / GPIO_S0_SC_86
SIO_I2C4_CLK / GPIO_S0_SC_87

G

R1010 1
@
0_0402_5%

USB_RCOMP

D

2

S

C1015

@EMC@
2
1 10P_0402_50V8J LPC_CLK_0

R1008 1
45.3_0402_1%

@
R1006
10K_0402_5%

2

1

<21>

GPIO_S5_31

1

D

2

G2

BJ29
BG29
BH30
BG30

GPIO_S0_SC_92
GPIO_S0_SC_93

T201@
T202@

For Touch Pad
+1.8VS
SOC_I2C2_DATA R1153 1

FH8065301546401_FCBGA131170
B0@

SOC_I2C2_CLK

2 2.2K_0402_5%

R1152 1

2 2.2K_0402_5%

G

5

+1.8VS

I2C2_SDA_TP

<23>

I2C2_SCL_TP

<23>

G

2

D

S

3
SOC_I2C2_DATA 4
Q81A
DMN63D8LDW_SOT363-6

A

1
6
Q81B
DMN63D8LDW_SOT363-6

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

D

S

SOC_I2C2_CLK

2014/04/12

Deciphered Date

Title

VLV-M SOC USB/LPC/SMBus

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

1

9

of

Rev
1.0
39

A


5

4

3

2

1

D

D

+1.35V_SOC
+SOC_VCC

USOC1G
AA27
AA29
AA30
AC27
AC29
AC30
AD27
AD29
AD30
AF27
AF29
AG27
AG29
AG30
P26
P27
U27
U29
V27
V29
V30
Y27
Y29
Y30

T194

AA22

TP2_CORE_VCC_S0iX

DRAM_VDD_S4_AD38
DRAM_VDD_S4_AF38
DRAM_VDD_S4_A48
DRAM_VDD_S4_AK38
DRAM_VDD_S4_AM38
DRAM_VDD_S4_AV41
DRAM_VDD_S4_AV42
DRAM_VDD_S4_BB46
DRAM_VDD_S4_BD49
DRAM_VDD_S4_BD52
DRAM_VDD_S4_BD53
DRAM_VDD_S4_BF44
DRAM_VDD_S4_BG51
DRAM_VDD_S4_BJ48
DRAM_VDD_S4_C51
DRAM_VDD_S4_D44
DRAM_VDD_S4_F49
DRAM_VDD_S4_F52
DRAM_VDD_S4_F53
DRAM_VDD_S4_H46
DRAM_VDD_S4_M41
DRAM_VDD_S4_M42
DRAM_VDD_S4_V38

DRAM_VDD_S4_Y38

CORE_VCC_S0IX_AD27
CORE_VCC_S0IX_AD29
CORE_VCC_S0IX_AD30
CORE_VCC_S0IX_AF27
CORE_VCC_S0IX_AF29
CORE_VCC_S0IX_AG27
CORE_VCC_S0IX_AG29
CORE_VCC_S0IX_AG30
CORE_VCC_S0IX_P26
CORE_VCC_S0IX_P27
CORE_VCC_S0IX_U27
CORE_VCC_S0IX_U29
CORE_VCC_S0IX_V27
CORE_VCC_S0IX_V29
CORE_VCC_S0IX_V30
CORE_VCC_S0IX_Y27
CORE_VCC_S0IX_Y29
CORE_VCC_S0IX_Y30

AD38
AF38
A48
AK38
AM38
AV41
AV42
BB46
BD49

BD52
BD53
BF44
BG51
BJ48
C51
D44
F49
F52
F53
H46
M41
M42
V38
Y38

1

1

B

BB8
P28
N28

VGFX_VSNS
VCORE_VSNS
VCORE_GSNS

1250mA

C1019 2
C1020 2
C1021 2
C1022 2

1
1
1
1

C

C1147 1
C1148 1

2 10U_0603_6.3V6M
2 10U_0603_6.3V6M

JUMP_43X118

2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M

0715 Add for CRT flicker

ICLK_V1P35_S3_F2_AG18

ICLK_V1P35_S3_F1_AJ19
VGA_V1P35_S3_F1_BD1

AG18
AJ19

VGA_V1P35_S3_F1

DRAM_V1P35_S0IX_F1_AD36
UNCORE_V1P35_S0IX_F2_AG32
UNCORE_V1P35_S0IX_F3_V36
UNCORE_V1P35_S0IX_F4_U36
UNCORE_V1P35_S0IX_F5_AA25

VGA_V1P35_S3_F1

C1023 1

4

R1084
8.06K_0402_1%

2 10U_0603_6.3V6M

AD36
AG32
V36
U36

OUT

IN

BYP

SHDN

1
2

1

3
2

G916T1UF_SOT23-5

C1179
1U_0402_6.3V6K

R1085
100K_0402_1%
B

AA25
<22,25,30,31,32>

UNCORE_V1P35_S0IX_F6_AF19
UNCORE_VNN_SENSE

UNCORE_V1P35_S0IX_F1_AG19
CORE_VCC_SENSE_P28 7 OF 13
CORE_VSS_SENSE_N28

5

GND

BD1

2

UNCORE_VNN_S3_AM22
UNCORE_VNN_S3_AK32
UNCORE_VNN_S3_AK30
UNCORE_VNN_S3_AK29
UNCORE_VNN_S3_AK27
UNCORE_VNN_S3_AK25
UNCORE_VNN_S3_AK24
UNCORE_VNN_S3_AK22
UNCORE_VNN_S3_AJ24
UNCORE_VNN_S3_AJ22
UNCORE_VNN_S3_AG24
UNCORE_VNN_S3_AG22
UNCORE_VNN_S3_AF24
UNCORE_VNN_S3_AF22
UNCORE_VNN_S3_AD22
UNCORE_VNN_S3_AC24
UNCORE_VNN_S3_AC22
UNCORE_VNN_S3_AA24

UNCORE_VNN_S3_AD24

+3VALW

U65

420mA

AF19
AG19

C1024 1
C1025 1
C1026 1
C1027 1
C1028 1
C1029 1
C1030 1
C1031 1
C1032 1
C1033 1

FH8065301546401_FCBGA131170
R1020
100_0402_1%

@EMC@ L63
2
1
HCB2012KF-121T50_2P

JP3 JP@

1

<33>
<33>
<33>

2

R1019
100_0402_1%
2

R1018
100_0402_1%

@EMC@ L62
2
1
HCB2012KF-121T50_2P

+1.35VS
AM22
AK32
AK30
AK29
AK27
AK25
AK24

AK22
AJ24
AJ22
AG24
AG22
AF24
AF22
AD22
AC24
AC22
AA24
AD24

+SOC_VCC

2 1U_0402_6.3V6K
2 .1U_0402_16V7K

TP2_CORE_VCC_S0IX

14A +SOC_VNN

+SOC_VNN

C1017 1
C1018 1

1

@

CORE_VCC_S0IX_AA27
CORE_VCC_S0IX_AA29
CORE_VCC_S0IX_AA30
CORE_VCC_S0IX_AC27
CORE_VCC_S0IX_AC29
CORE_VCC_S0IX_AC30

+1.35V_L

@EMC@ L61
2
1
HCB2012KF-121T50_2P

1

C

20mil

2

12A

2

B0@

2

2
2
2
@2
2
2
2
2
2

22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K

VOUT

2
1
R1087
36K_0402_5%

SUSP#

1

2

= 1.25 (1 + R1/R2).

C1181
.1U_0402_16V7K

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

VLV-M SOC Power

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

1

10

of

Rev
1.0

39


5

4

3

2

1

D

D

USOC1H
+1.0VALW
UNCORE_V1P0_G3 1uF*4

USB3_V1P0_G3 0.01uF*1

C1034
C1035
C1036
C1037

1
1

1
1

2
2
2
2

C1039

1

2 0.01U_0402_16V7K

1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K

+1.0VS
C

DRAM_V1P0_S0iX 1uF*4

C1043
C1044
C1046
C1047

1

1
1
1

2
2
2
2

1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K

DDI_V1P0_S0iX 1uF*4

C1048
C1049
C1050
C1052

1
1
1
1

2
2
2
2

1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K

UNCORE_V1P0_S0iX 22uF*3
1uF*2

PCIE_SATA_V1P0_S3 1uF*1
UNCORE_V1P0_S3 1uF*1
PCIE_V1P0_S3 1uF*1
VGA_V1P0_S3 1uF*1
USB_V1P0_S3 0.1uF*1
USB3DEV_V1P0_S3 0.01uF*1
GPIO_V1P0_S3 1uF*1
SVID_V1P0_S3 1uF*1

C1056 1
C1057 1
C1059 1
C1060 1
C1061 1

2
2
2
2
2

22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K

C1062 1
C1064 1
C1066 1
C1068 1
C1069 1
C1070 1
C1071 1
C1072 1

2
2
2
2
2
2
2
2

1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K
0.01U_0402_16V7K

1U_0402_6.3V6K
1U_0402_6.3V6K

B

U22
V22
C5
B6
Y19
C3

V32
BJ6
AD35
AF35
AF36
AA36
AJ36
AK35
AK36
Y35
Y36
AK19
AK21
AJ18
AM16
AN29
AN30
V24

Y22
Y24
AF16
AF18
Y18
G1
AK18
AM18
AM21
AN21
AN18
AN19
AF21
AG21
M14
U18
U19
AN25

Follow CRBv1.15
325mA

UNCORE_V1P0_G3_U22
UNCORE_V1P0_G3_V22
UNCORE_V1P0_G3_C5
UNCORE_V1P0_G3_B6

1000mA
CORE_V1P0_S3_AC32
CORE_V1P0_S3_Y32

USB3_V1P0_G3_Y19
USB3_V1P0_G3_C3

2750mA
SVID_V1P0_S3_V32
VGA_V1P0_S3_BJ6
DRAM_V1P0_S0IX_AD35
DRAM_V1P0_S0IX_AF35
DRAM_V1P0_S0IX_AF36
DRAM_V1P0_S0IX_AA36
DRAM_V1P0_S0IX_AJ36
DRAM_V1P0_S0IX_AK35
DRAM_V1P0_S0IX_AK36
DRAM_V1P0_S0IX_Y35
DRAM_V1P0_S0IX_Y36
DDI_V1P0_S0IX_AK19
DDI_V1P0_S0IX_AK21
DDI_V1P0_S0IX_AJ18
DDI_V1P0_S0IX_AM16
VIS_V1P0_S0IX_AN29
VIS_V1P0_S0IX_AN30
VIS_V1P0_S0IX_V24
VIS_V1P0_S0IX_Y22
VIS_V1P0_S0IX_Y24
UNCORE_V1P0_S3_AF16
UNCORE_V1P0_S3_AF18
UNCORE_V1P0_S3_Y18
UNCORE_V1P0_S3_G1
PCIE_V1P0_S3_AK18

PCIE_V1P0_S3_AM18
PCIE_V1P0_S3_AM21
PCIE_V1P0_S3_AN21
PCIE_SATA_V1P0_S3_AN18
SATA_V1P0_S3_AN19
UNCORE_V1P0_S0IX_AF21
UNCORE_V1P0_S0IX_AG21
USB_V1P0_S3_M14
USB_V1P0_S3_U18
USB_V1P0_S3_U19
GPIO_V1P0_S3_AN25

CORE_V1P05_S3_AA33
CORE_V1P05_S3_AF33
CORE_V1P05_S3_AG33
CORE_V1P05_S3_AG35
CORE_V1P05_S3_U33
CORE_V1P05_S3_U35
CORE_V1P05_S3_V33

F1
TP_CORE_V1P05_S4

AF30

AA33
AF33
AG33
AG35
U33

U35
V33

C1038 1

2 0.47U_0402_6.3V6K

C1040 1
C1041 1
C1042 1

2 1U_0402_6.3V6K
2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

CORE_V1P05_S3 1uF*3
+1.8VALW
C

UNCORE_V1P8_G3_U24
PCU_V1P8_G3_V25
USB_V1P8_G3_N20
65mA PMU_V1P8_G3_U25
UNCORE_V1P8_G3_AA18

U24
V25
N20
U25
AA18

C1045 1

PMC_V1P8_G3 1uF*1

2 1U_0402_6.3V6K

+1.8VS

10mA
UNCORE_V1P8_S3_AM30
UNCORE_V1P8_S3_AN32
UNCORE_V1P8_S3_U38

58mA
HDA_V1P5_S3_AM32

50mA PCU_V3P3_G3_N22
USB_V3P3_G3_N18
USB_V3P3_G3_P18

33mA
VGA_V3P3_S3_AN24
SD3_V1P8V3P3_S3_AN27
LPC_V1P8V3P3_S3_AM27

35mA
USB_HSIC_V1P2_G3_V18

T195

@

+1.05VS

AC32
Y32

RESERVED_F1

VSS_AD16
VSS_AD18

AM30
AN32
U38

C1051 1
C1053 1
C1054 1
C1055 1

2
2
2
@2

1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K

UNCORE_V1P8_S3 1uF*4
+1.5VS

AM32
C1058 1

2 1U_0402_6.3V6K

+3VALW

N22 +3VALW_SOC
2 RS@
1
R1022
0_0402_5%
2 .1U_0402_16V7K
C1063 1
2 1U_0402_6.3V6K
C1065 1
2 1U_0402_6.3V6K
C1067 1

USB_V3P3_G3 0.1uF*1
USB_ULPI_V1P8_S3 1uF*1
PCU_V3P3_G3 1uF*1

N18
P18

AN24

+3VS

2 RS@
1
R1023
0_0402_5%
1
2
C1073
1U_0402_6.3V6K
AM27 +1.8VS_3.3VS LPC 2 TPM@ 1
R1031
0_0402_5%
2 NTPM@ 1
R1032
0_0402_5%
V18
1
2
C1075
1U_0402_6.3V6K
+3VS_SOC

AN27

AD16
AD18

TP_CORE_V1P05_S4_AF30

C1074 1

HDA_LPE_V1P5V1P8_S3 1uF*1

+3VS

VGA_V3P3_S3 1uF*1

+1.8VS
B

+1.0VALW
USB_HSIC_V1P2_G3 1uF*1

Disable HSIC
If the USB HSIC is not used, pin V18 can be connected
to either +V1P2A or +V1P0A.

2 1U_0402_6.3V6K
@

Pop when use +1.2VALW

8 OF 13
FH8065301546401_FCBGA131170
B0@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

VLV-M SOC Power

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

1

11

of

Rev
1.0
39


5

4

3

2

1

D

D

C

C

USOC1I
A11
A15
A19
A23
A27
A31
A35
A39
A43
A47
AA1
AA16
AA19
AA21
AA3
AA32
AA35
AA38

AA53
AB10
AB4
AB41
AB45
AB47
AB48
AB50
AB51
AB6
AC16
AC18
AC19
AC21
AC25
AC33
AC35
B2
A6
A52
A51
A5
A49
A3
BH53
BH52
BH2
BH1
BG53
E53

B

U16
AN16

VSS_A11
VSS_AC36
VSS_A15
VSS_AC38
VSS_A19
VSS_AD19
VSS_A23
VSS_AD21
VSS_A27
VSS_AD25
VSS_A31
VSS_AD32
VSS_A35
VSS_AD33
VSS_A39
VSS_AD47
VSS_A43
VSS_AD7
VSS_A47
VSS_AE1
VSS_AA1
VSS_AE11
VSS_AA16
VSS_AE12

VSS_AA19
VSS_AE14
VSS_AA21
VSS_AE3
VSS_AA3
VSS_AE4
VSS_AA32
VSS_AE40
VSS_AA35
VSS_AE42
VSS_AA38
VSS_AE43
VSS_AA53
VSS_AE45
VSS_AB10
VSS_AE46
VSS_AB4
VSS_AE48
VSS_AB41
VSS_AE50
VSS_AB45
VSS_AE51
VSS_AB47
VSS_AE53
VSS_AB48
VSS_AE6
VSS_AB50
VSS_AE8
VSS_AB51
VSS_AE9

VSS_AB6
VSS_AF10
VSS_AC16
VSS_AF12
VSS_AC18
VSS_AF25
VSS_AC19
VSS_AF32
VSS_AC21
VSS_AF47
VSS_AC25
VSS_AG16
VSS_AC33
VSS_AG25
VSS_AC35 9 OF 13VSS_AG36
VSS_B2
VSS_B52
VSS_A6
VSS_B53
VSS_A52
VSS_BE1
VSS_A51
VSS_BE53
VSS_A5
VSS_BG1
VSS_A49
VSS_BJ2
VSS_A3
VSS_BJ3
VSS_BH53

VSS_BJ5
VSS_BH52
VSS_BJ49
VSS_BH2
VSS_BJ51
VSS_BH1
VSS_BJ52
VSS_BG53
VSS_C1
VSS_E53
VSS_C53
VSS_E1

USOC1J
AC36
AC38
AD19
AD21
AD25
AD32
AD33
AD47
AD7
AE1
AE11
AE12
AE14
AE3
AE4
AE40

AE42
AE43
AE45
AE46
AE48
AE50
AE51
AE53
AE6
AE8
AE9
AF10
AF12
AF25
AF32
AF47
AG16
AG25
AG36
B52
B53
BE1
BE53
BG1
BJ2
BJ3
BJ5
BJ49
BJ51
BJ52

C1
C53
E1

AG38
AH4
AH41
AH45
AH7
AH9
AJ1
AJ16
AJ21
AJ25
AJ27
AJ29
AJ3
AJ30
AJ32
AJ33
AJ35
AJ38
AJ53
AK10
AK14
AK16
AK33
AK41
AK44
AM12

AM19
AM24
AM25
AM29
AM33
AM35
AM36
AM40
M28

VSS_AG38
VSS_AH47
VSS_AH4
VSS_AH48
VSS_AH41
VSS_AH50
VSS_AH45
VSS_AH51
VSS_AH7
VSS_AH6
VSS_AH9
VSS_AM44
VSS_AJ1
VSS_AM51
VSS_AJ16
VSS_AM7
VSS_AJ21
VSS_AN1
VSS_AJ25
VSS_AN11

VSS_AJ27
VSS_AN12
VSS_AJ29
VSS_AN14
VSS_AJ3
VSS_AN22
VSS_AJ30
VSS_AN3
VSS_AJ32
VSS_AN33
VSS_AJ33
VSS_AN35
VSS_AJ35
VSS_AN36
VSS_AJ38
VSS_AN38
VSS_AJ53
VSS_AN40
VSS_AK10
VSS_AN42
VSS_AK14
VSS_AN43
VSS_AK16
VSS_AN45
VSS_AK33
VSS_AN46
VSS_AK41
VSS_AN48
VSS_AK44
VSS_AN49

VSS_AM12
VSS_AN5
VSS_AM19
VSS_AN51
VSS_AM24
VSS_AN53
VSS_AM25
VSS_AN6
VSS_AM29
VSS_AN8
VSS_AM33
VSS_AN9
VSS_AM35
VSS_AP40
VSS_AM36
VSS_AT12
VSS_AM40
VSS_AT16
VSS_M28 10 OF 13 VSS_AT19

USOC1K
AH47
AH48
AH50
AH51
AH6
AM44
AM51
AM7
AN1

AN11
AN12
AN14
AN22
AN3
AN33
AN35
AN36
AN38
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN5
AN51
AN53
AN6
AN8
AN9
AP40
AT12
AT16
AT19

AT24
AT27
AT30

AT35
AT38
AT4
AT47
AT52
AU1
AU24
AU3
AU30
AU38
AU51
AV12
AV13
AV14
AV18
AV19
AV24
AV27
AV30
AV35
AV38
AV47
AV51
AV7
AW13
AW19
AW27
AW3
AW35
AY10

AY22
AY32

USOC1L

VSS_AT24
VSS_AY36
VSS_AT27
VSS_AY4
VSS_AT30
VSS_AY50
VSS_AT35
VSS_AY9
VSS_AT38
VSS_BA14
VSS_AT4
VSS_BA19
VSS_AT47
VSS_BA22
VSS_AT52
VSS_BA27
VSS_AU1
VSS_BA32
VSS_AU24
VSS_BA35
VSS_AU3
VSS_BA40
VSS_AU30
VSS_BA53
VSS_AU38

VSS_BB19
VSS_AU51
VSS_BB27
VSS_AV12
VSS_BB35
VSS_AV13
VSS_BC20
VSS_AV14
VSS_BC22
VSS_AV18
VSS_BC26
VSS_AV19
VSS_BC28
VSS_AV24
VSS_BC32
VSS_AV27
VSS_BC34
VSS_AV30
VSS_BC42
VSS_AV35
VSS_BD19
VSS_AV38
VSS_BD24
VSS_AV47
VSS_BD27
VSS_AV51
VSS_BD30
VSS_AV7
VSS_BD35
VSS_AW13

VSS_BE19
VSS_AW19
VSS_BE2
VSS_AW27
VSS_BE35
VSS_AW3
VSS_BE8
VSS_AW35
VSS_BF12
VSS_AY10
VSS_BF16
VSS_AY22
VSS_BF24
VSS_AY32 11 OF 13
VSS_BF38

AY36
AY4
AY50
AY9
BA14
BA19
BA22
BA27
BA32
BA35
BA40
BA53
BB19
BB27

BB35
BC20
BC22
BC26
BC28
BC32
BC34
BC42
BD19
BD24
BD27
BD30
BD35
BE19
BE2
BE35
BE8
BF12
BF16
BF24
BF38

BF30
BF36
BF4
BG31
BG34
BG39
BG42
BG45

BG49
BJ11
BJ15
BJ19
BJ23
BJ27
BJ31
BJ35
BJ39
BJ43
BJ47
BJ7
C14
C31
C34
C39
C42
C45
C49
D12
D16
D24
D30
D36
D38
E19
E35

VSS_BF30
VSS_BF36

VSS_BF4
VSS_BG31
VSS_BG34
VSS_BG39
VSS_BG42
VSS_BG45
VSS_BG49
VSS_BJ11
VSS_BJ15
VSS_BJ19
VSS_BJ23
VSS_BJ27
VSS_BJ31
VSS_BJ35
VSS_BJ39
VSS_BJ43
VSS_BJ47
VSS_BJ7
VSS_C14
VSS_C31
VSS_C34
VSS_C39
VSS_C42
VSS_C45
VSS_C49
VSS_D12
VSS_D16
VSS_D24
VSS_D30
VSS_D36

VSS_D38
VSS_E19
VSS_E35 12 OF 13

USOC1M
VSS_E8
VSS_F19
VSS_F2
VSS_F24
VSS_F27
VSS_F30
VSS_F35
VSS_F5
VSS_F7
VSS_G10
VSS_G20
VSS_G22
VSS_G26
VSS_G28
VSS_G32
VSS_G34
VSS_G42
VSS_H19
VSS_H27
VSS_H35
VSS_J1
VSS_J16
VSS_J19
VSS_J22
VSS_J27

VSS_J32
VSS_J35
VSS_J40
VSS_J53
VSS_K14
VSS_K22
VSS_K32
VSS_K36
VSS_K4
VSS_K50

E8
F19
F2
F24
F27
F30
F35
F5
F7
G10
G20
G22
G26
G28
G32
G34
G42
H19
H27

H35
J1
J16
J19
J22
J27
J32
J35
J40
J53
K14
K22
K32
K36
K4
K50

K9
L13
L19
L27
L35
M19
M26
M27
M34
M35
M38
M47
M51

N1
N16
N38
N51
P13
P16
P19
P20
P24
P32
P35
P38
P4
P47
P52
P9
T40
U1
U11
U12
U14
U21

VSS_K9
VSS_L13
VSS_L19
VSS_L27
VSS_L35
VSS_M19
VSS_M26

VSS_M27
VSS_M34
VSS_M35
VSS_M38
VSS_M47
VSS_M51
VSS_N1
VSS_N16
VSS_N38
VSS_N51
VSS_P13
VSS_P16
VSS_P19
VSS_P20
VSS_P24
VSS_P32
VSS_P35
VSS_P38
VSS_P4
VSS_P47
VSS_P52
VSS_P9
VSS_T40
VSS_U1
VSS_U11
VSS_U12
VSS_U14
VSS_U21 13 OF 13

VSS_U3

VSS_U30
VSS_U32
VSS_U40
VSS_U42
VSS_U43
VSS_U45
VSS_U46
VSS_U48
VSS_U49
VSS_U5
VSS_U51
VSS_U53
VSS_U6
VSS_U8
VSS_U9
VSS_V12
VSS_V16
VSS_V19
VSS_V21
VSS_V35
VSS_V40
VSS_V44
VSS_V51
VSS_V7
VSS_Y10
VSS_Y14
VSS_Y16
VSS_Y21
VSS_Y25
VSS_Y33

VSS_Y41
VSS_Y44
VSS_Y7
VSS_Y9

FH8065301546401_FCBGA131170

FH8065301546401_FCBGA131170

FH8065301546401_FCBGA131170

FH8065301546401_FCBGA131170

B0@

B0@

B0@

B0@

U3
U30
U32
U40
U42
U43
U45
U46
U48

U49
U5
U51
U53
U6
U8
U9
V12
V16
V19
V21
V35
V40
V44
V51
V7
Y10
Y14
Y16
Y21
Y25
Y33
Y41
Y44
Y7
Y9

B

USB_VSSA_U16

VSSA_AN16
FH8065301546401_FCBGA131170
B0@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

VLV-M SOC GND

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

1

12

of

Rev
1.0
39


A

B

C

+DDR_A_VREF_DQ

+1.35V_L

DDR_A_D0
DDR_A_D1
DDR_A_DM0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
1

DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19

All VREF traces should
have 10 mil trace width

DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

<5>

DDR_A_CKE0

<5>

DDR_A_BS2
DDR_A_MA12
DDR_A_MA9

2

DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<5>
<5>

DDR_A_CLK0
DDR_A_CLK0#

<5>

DDR_A_BS0

<5>
<5>

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA10

DDR_A_MA13
<5>

DDR_A_CS2#

DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41

3

DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48

DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59

+3VS

1

1

2

2

RS@
R212
0_0402_5%

C125
.1U_0402_16V7K

0_0402_5%

4

RS@
R211

1

2

+0.675VS

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109

111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169

171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS

DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2

VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS

DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD

SA1
VTT
GND1
BOSS1

E

+1.35V_L

CONN@
JDIMM1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37

39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

D

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS

DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
A15
A14

VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38

DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA

SCL
VTT
GND2
BOSS2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110

112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170

172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208

LCN_DAN06-K4406-0100
Part Number = SP07000N300
LCN_DAN06-K4406-0100_204P

<Address: SA1:SA0=00 (A0H)>

DIMM_1 STD H:4mm

DDR_A_D4
DDR_A_D5

DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D[0..63]

DDR_A_D6
DDR_A_D7

DDR_A_MA[0..15]
DDR_A_DM[0..7]

DDR_A_D12
DDR_A_D13

<5>
<5>
<5>
<5>
<5>
1

DDR_A_DM1
DDR_A_RST#

<5>

DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21

DDR_A_RST#

DDR_A_DM2

EMC@
2.1U_0402_16V7K
C1077 1

FOR EMI/ESD Require 01/15

DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3

Signal voltage level = 0.675 V
PLACE TWO 4.7K RESISTORS CLOSE TO
DIMMS ON DIMM_VREF_CA / DIMM_VREF_DQ
Decoupling caps are needed; one 0.1 µF placed close to VREF pins of each DDR3 SODIMM.

DDR_A_D30
DDR_A_D31

DDR_A_CKE2

<5>

DDR_A_MA15
DDR_A_MA14

+1.35V_L

DDR_A_MA11
DDR_A_MA7

1

DDR_A_MA6
DDR_A_MA4

1

DDR_A_MA2
DDR_A_MA0

+DDR_A_VREF_DQ
+1.35V

2
R1027
4.7K_0402_1%
2
R1028

4.7K_0402_1%

2

C1076
.1U_0402_16V7K

+1.35V_L

DDR_A_CS0#
DDR_A_ODT0

<5>
<5>

DDR_A_ODT2

<5>

+DDR_A_VREF_CA
JP5 JP@

1

2

R1029
4.7K_0402_1%
1
2

R1030
4.7K_0402_1%

JUMP_43X118

1

2

C1078
.1U_0402_16V7K

+DDR_A_VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A_DM4

Layout Note:
Place near JDIMM1

DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45

+1.35V_L

3

+1.35V

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61

C111
C112
C113
C114

1
1
1
1

2
2
2
2

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

C110
C109
C108
C107
C115
C116
C117
C164

1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

2 .1U_0402_16V7K
C167 1@EMC@
2 .1U_0402_16V7K
C166 1@EMC@

DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

+0.675VS

EC_SMB_DA2
EC_SMB_CK2

<14,19,22,9>
<14,19,22,9>

+0.675VS

C123 1

2 10U_0603_6.3V6M

C124 1
C122 1

2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

Channel A

4

Layout Note:
Place near JDIMM1.203,204

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

B

DDR3L DIMMA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

2

L60 @EMC@
1
2
HCB2012KF-221T30_2P

DDR_A_CLK2 <5>
DDR_A_CLK2# <5>
DDR_A_BS1 <5>
DDR_A_RAS# <5>

+1.35V_L
L59 @EMC@
1

2
HCB2012KF-221T30_2P

1

C

D

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

E

13

of

Rev
1.0
39


A

B

+DDR_B_VREF_DQ

+1.35V_L

DDR_B_D0
DDR_B_D1
DDR_B_DM0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
1

DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19

All VREF traces should
have 10 mil trace width

DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26

DDR_B_D27

<5>

DDR_B_CKE0

<5>

DDR_B_BS2

2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
<5>
<5>

DDR_B_CLK0
DDR_B_CLK0#
DDR_B_MA10

<5>

DDR_B_BS0

<5>

<5>

DDR_B_WE#
DDR_B_CAS#

<5>

DDR_B_CS2#

DDR_B_MA13

DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
3

DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51

+3VS
2

DDR_B_D56
DDR_B_D57

R229
10K_0402_5%

DDR_B_DM7

1

DDR_B_D58
DDR_B_D59

+3VS
+0.675VS

RS@
R231
0_0402_5%

2

CKE0
VDD1
NC1
BA2

VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32

DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD

SA1
VTT1
G1

E

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17

DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12

BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53

VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
G2

2
4
6
8
10
12
14
16
18

20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76

78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136

138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196

198
200
202
204

DDR_B_D4
DDR_B_D5

DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D[0..63]

DDR_B_D6
DDR_B_D7

DDR_B_MA[0..15]
DDR_B_DM[0..7]

DDR_B_D12
DDR_B_D13

<5>
<5>
<5>
<5>
<5>

1

DDR_B_DM1
DDR_B_RST#

<5>

DDR_B_D14
DDR_B_D15
DDR_B_RST#
DDR_B_D20
DDR_B_D21

1
2
C84
.1U_0402_16V7K

FOR EMI/ESD Require 01/15

DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29

+1.35V_L

+DDR_B_VREF_DQ

1

2
R1069
4.7K_0402_1%
1
2
R1067
4.7K_0402_1%

DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

DDR_B_CKE2

1

2

C128
.1U_0402_16V7K

<5>
+1.35V_L

DDR_B_MA15
DDR_B_MA14

+DDR_B_VREF_CA

1
DDR_B_MA11
DDR_B_MA7
1
DDR_B_MA6
DDR_B_MA4

2
2

R1070
4.7K_0402_1%
2
R1068
4.7K_0402_1%

1

2

C142
.1U_0402_16V7K

DDR_B_MA2
DDR_B_MA0
DDR_B_CLK2 <5>
DDR_B_CLK2# <5>

+1.35V_L

DDR_B_BS1 <5>
DDR_B_RAS# <5>
DDR_B_CS0#
DDR_B_ODT0

<5>
<5>

DDR_B_ODT2

<5>

+DDR_B_VREF_CA
DDR_B_D36
DDR_B_D37

C133
C134
C135
C136

1
1
1
1

2
2

2
2

10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M

C129
C130
C131
C132
C137
C138
C139

1
1
1
1
1
1
1

2
2
2
2
2
2

2

.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K

DDR_B_DM4
DDR_B_D38
DDR_B_D39

Layout Note:
Place near JDIMM2

DDR_B_D44
DDR_B_D45

3

+0.675VS

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47

C143 1

2 10U_0603_6.3V6M

DDR_B_D52
DDR_B_D53

C145 1
C146 1

2 1U_0402_6.3V6K
2 1U_0402_6.3V6K

DDR_B_DM6
DDR_B_D54
DDR_B_D55

Layout Note:
Place near JDIMM2.203,204

DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63

EC_SMB_DA2
EC_SMB_CK2

<13,19,22,9>

<13,19,22,9>

+0.675VS

206

TYCO_2-2013287-1
Part Number = SP07000KW00
PCB Footprint = TYCO_2-2013287-1_204P

Channel B

4

1

C147
.1U_0402_16V7K

73
75
77
79
81
83
85
87
89
91
93

95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153

155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

VREF_DQ
VSS2
DQ0
DQ1

VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26

DQ27
VSS25

D

+1.35V_L

CONN@
JDIMM2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

205

2
1

4

C

<Address: SA0:SA1=10 (A2H)>
SA0/SA1 Follow INTEL demo board

DIMM_2 REV H:4mm

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

DDR3L DIMMB

C

D

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

E

14

of

Rev
1.0
39


A

B

C

+3VS

5
4
1

C140
1U_0402_6.3V6K

SM010014520 3000ma
220ohm@100mhz
DCR 0.04

+LCDVDD
U8
VOUT

W=60mils

1

B+

VIN
GND

W=60mils

1

2

VIN
EN

2

3

EMC@
+INVPWR_B+
L11
HCB2012KF-221T30_2P
1
2

C367
4.7U_0603_6.3V6K

<6>

R959
0_0402_5%
1
2
1

W=60mils

1

1

2

2

@EMC@
C364
1000P_0402_50V7K
<6>
<22>

INVT_PWM_SOC
EC_BKOFF#

1
2
C549
@EMC@
220P_0402_50V7K
1
2
C528
@EMC@
220P_0402_50V7K

ENVDD

<22>
+1.8VS
1

2

EDP_AUXP_C

1

1 100K_0402_5%

+LCDVDD

2 100K_0402_5%

@

I2C TS

<9> I2C5_SDA_PNL
<9> I2C5_SCL_PNL

2
1
D
G
3

S

EDP_HPD_CONN

<6> EDP_TXP0
<6> EDP_TXN0
<6> EDP_TXP1
<6> EDP_TXN1

1

2

<6> EDP_AUXN
<6> EDP_AUXP

Intel recommends having a pull-up resistor of 100 kΩ for
AUXN and a pull-down resistor of 100 kΩ for AUXP between
the AC capacitor and the connector, to assist source
detection by the sink device.

EDP_HPD#

Q13
2N7002K_SOT23-3

TS_EN_1

TS_RST#

TS_RST#

R383
10K_0402_5%

2

EDP_HPD_CONN

+LCDVDD

@
EDP_AUXN_C R1063
R1062

<6>

JLVDS1

W=60mils
+INVPWR_B+

@EMC@
C365
68P_0402_50V8J

G5243AT11U_SOT23-5

2

E

LCD/ LED PANEL Conn.

LCD POWER CIRCUIT
1

D

C377 1
C376 1

2 .1U_0402_16V7K EDP_AUXN_C
2 .1U_0402_16V7K EDP_AUXP_C

C371 1
C372 1

2 .1U_0402_16V7K EDP_TXP0_C
2 .1U_0402_16V7K EDP_TXN0_C

C373 1
C374 1

2 .1U_0402_16V7K EDP_TXP1_C
2 .1U_0402_16V7K EDP_TXN1_C
TS_INT#

+TS_PWR

2

R364
100K_0402_5%

<9>

USB20_P3

<9>

USB20_N3

USB20_P3
USB20_N3

R427 1
R428 1
L27
3
3
2

2

RS@ 2 0_0402_5%
RS@ 2 0_0402_5%
4
1

4

<9> USB20_P2
<9> USB20_N2

USB TS

+3VS
USB20_P3_CAMERA

1

2 RS@
1
+3VS_Camcra
0_0402_5%
R1162 USB20_P3_CAMERA
USB20_N3_CAMERA

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

USB20_N3_CAMERA

1
2
3
4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37

38
39
40

G1
G2
G3
G4
G5
G6

41
42
43
44
45
46

2

E-T_0871K-F40N-00L
SP010011Z00
CONN@

WCM2012F2SF-670T04_0805
@EMC@

+TS_PWR

For Touch Panel

+5VS

3

2 TSI@
1 I2C5_SDA_PNL
2.2K_0402_5%
R1147
2 TSI@
1 I2C5_SCL_PNL
2.2K_0402_5%
R1150
1 TSI@
2
TS_INT#
10K_0402_5%
R635

+TS_PWR

1

2
R1145
0_0603_5%

1 TSI@
10K_0402_5%

2

R636

3

TS_RST#

Camera reserve

pin define,need to confirm

+3VS

1

2
@
R1146
0_0603_5%

<22>

R1033 1

TS_EN

RS@ 2 0_0402_5%

TS_EN_1

+3VS

R431 1
R430 1

@
@

2 0_0402_5%
2 0_0402_5%
JCAM1

USB20_P3

2

USB20_N3

3

2

1

1

4
3
4
L28 @EMC@
WCM2012F2SF-670T04_0805

USB20_P3_EXCA
USB20_N3_EXCA

1
USB20_P3_EXCA 2
USB20_N3_EXCA 3
4

1
2
3
4

G1
G2

5
6

ACES_88266-04001
SP02000K200
CONN@

1

+1.8VS

4

4

2

3

1

S

D

TS_INT_R#

TS_INT_R#

G

<8>

2

TSI@ R634
10K_0402_5%

TS_INT#

TSI@ Q78
MESS138W-G_SOT323-3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

eDP CONN.

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

E

15

of

Rev
1.0
39


A

B

W=40mils

+5VS

C

D

U52

WCM-2012-900T_0805
HDMI_C_CLK+ L53
@EMC@1

3

OUT
1

4

HDMI_C_CLK-

1

2 RS@

R368

+HDMI_5V_OUT

1

IN
2

GND

2

C378
.1U_0402_16V7K

AP2330W-7_SC59-3

HDMI_TX1HDMI_TX1+
HDMI_TX2HDMI_TX2+

C381
C382
C379
C380

2
2
2
2

1
1
1
1

.1U_0402_16V7K HDMI_C_TX1.1U_0402_16V7K HDMI_C_TX1+
.1U_0402_16V7K HDMI_C_TX2.1U_0402_16V7K HDMI_C_TX2+

<6>

<6>
<6>
<6>

HDMI_TX0HDMI_TX0+
HDMI_CLKHDMI_CLK+

C383
C384
C385
C386

2
2
2
2

1
1
1
1

.1U_0402_16V7K HDMI_C_TX0.1U_0402_16V7K HDMI_C_TX0+
.1U_0402_16V7K HDMI_C_CLK.1U_0402_16V7K HDMI_C_CLK+

3

1

2

3

HDMI_R_CK-

2

HDMI_R_CK+

1 0_0402_5%

R370

2 RS@

1 0_0402_5%

4

3

1

2

3

HDMI_R_D0-

2

HDMI_R_D0+

R371

2 RS@

1 0_0402_5%

R372

2 RS@

1 0_0402_5%

4

HDMI_C_TX1-

4

2 RS@

WCM-2012-900T_0805
@EMC@1
HDMI_C_TX0+ L54

<6>
<6>
<6>

<6>

1 0_0402_5%

R369

4

HDMI_C_TX0-

E

4

WCM-2012-900T_0805
HDMI_C_TX1+ L55
@EMC@1

3

1

2

3

HDMI_R_D1-

2

HDMI_R_D1+

R373

2 RS@

1 0_0402_5%

R374

2 RS@

1 0_0402_5%

1

2

2

+1.8VS

RP15
HDMI_DDCDATA
HDMI_DDCCLK
HDMI_SDATA
HDMI_SCLK

5
6

7
8

4

HDMI_C_TX2-

+HDMI_5V_OUT

4
3
2
1

4

WCM-2012-900T_0805
@EMC@1
HDMI_C_TX2+ L56

1

2

2 RS@

R375

2.2K_0804_8P4R_5%

3

3

HDMI_R_D2-

2

HDMI_R_D2+

1 0_0402_5%

G

5

+1.8VS

G

2

S

3
HDMI_SCLK
Q82A
DMN63D8LDW_SOT363-6
D

4

HDMI_DDCCLK

1

6
Q82B
DMN63D8LDW_SOT363-6

HDMI_SDATA

2
2
2
2

619_0402_1%
619_0402_1%
619_0402_1%
619_0402_1%

HDMI_C_TX0HDMI_C_TX0+
HDMI_C_CLKHDMI_C_CLK+

R1075 1
R1076 1
R1077 1
R1078 1

2
2
2
2

619_0402_1%
619_0402_1%
619_0402_1%
619_0402_1%

D

HDMI_DDCDATA

S

<6>

R1071 1
R1072 1
R1073 1
R1074 1

HDMI_GND

<6>

HDMI_C_TX1HDMI_C_TX1+
HDMI_C_TX2HDMI_C_TX2+

3

3

3
D

G

5

+3VS

S

4

Q14A
DMN66D0LDW-7_SOT363-6

1

+1.8VS

HDMI connector

R376
10K_0402_5%

JHDMI1

2

+HDMI_5V_OUT

HDMI_HPD#

HDMI_SDATA
HDMI_SCLK
2

HDMI_HPD

D
S

1

1

3

G

Q14B
DMN66D0LDW-7_SOT363-6

2

6

<6>

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HDMI_HPD

HDMI_R_CKR121
100K_0402_5%

2

HDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1-

1

D2
@EMC@
YSLC05CH_SOT23-3

HDMI_R_D1+
HDMI_R_D2-

Reserved for ESD

4

HDMI_R_D2+

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKCK_shield
CK+
D0D0_shield
D0+

D1D1_shield
D1+
GND
D2GND
D2_shield GND
D2+
GND

20
21
22
23
4

SUYIN_100042GR019M23MZR
DC232001I00
CONN@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

HDMI CONN.

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

E

16

of

Rev
1.0
39


A

B

C

D

E

1

1

+HDMI_5V_OUT

07/05 : ripple reduce

1

C450
.1U_0402_16V7K

Video Filter

W=40mils

CRT Connector

T196
@

2

JCRT1
L42 EMC@
BLM15BB470SN1D_2P
1
2
L45 EMC@
BLM15BB470SN1D_2P
1
2
L46 EMC@
BLM15BB470SN1D_2P
1
2

77MHz@1920x1200x60Hz
<6>

CRT_R

<6>

CRT_G

<6>

CRT_B

2

2

CRT_DATA
CRT_G_2
CRT_B_2

1

2

1

2

C616 EMC@
10P_0402_50V8J

150_0804_8P4R_1%

2

1

CRT_R_2

C618 EMC@
10P_0402_50V8J

1
2
3
4

C647 EMC@
10P_0402_50V8J

8
7
6
5

1

C611 EMC@
15P_0402_50V8J

CRT_R
CRT_G
CRT_B

1

C615 EMC@
15P_0402_50V8J

C648 EMC@
15P_0402_50V8J

RP50

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

@ T206
@T206

1

CRT_CLK
2

G
G

16
17

CCM_070546HR015M25FZR
DC060005810
CONN@

2

2

+HDMI_5V_OUT
CRT_HSYNC_B
U24
1

74kHz@1920x1200x60Hz
<6>

2

CRT_HSYNC

3

1

60Hz@1920x1200x60Hz
<6>

2

CRT_VSYNC

3

OE

Vcc

1

5

2

@EMC@
C448
10P_0402_50V8J

IN A
GND OUT Y

4

CRT_VSYNC_B
1

M74VHC1GT125DF2G_SC70-5
U23
5
OE
Vcc

2

@EMC@
C449
10P_0402_50V8J

IN A
GND OUT Y

4

M74VHC1GT125DF2G_SC70-5
3

3

2

+3VS

G

+3VS

S

6

CRT_DATA
CRT_DDC_DATA
CRT_DDC_CLK
CRT_DATA
CRT_CLK

Q27B
DMN66D0LDW-7_SOT363-6
G

4

3

5
6
7
8

4

3
2
1

CRT_CLK

D

CRT_DDC_CLK

CRT_DDC_CLK

S

<6>

+HDMI_5V_OUT

RP42

D

1

CRT_DDC_DATA

CRT_DDC_DATA

5

<6>

2.2K_0804_8P4R_5%

Q27A
DMN66D0LDW-7_SOT363-6

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

CRT CONN.

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

E

17

of

Rev
1.0
39

5

4

+3VALW

3

2

1

+3V_LAN
@
R238 2

60mil

60mil

U67

+REGOUT

1

2

1

2

1

2

D

Place near Pin 11,32,48

The trace length
from C to
PIN35(VDDREG)
must < 200mils.

+3V_LAN
1

+3V_LAN Rising time must >0.5ms and <100ms

2

Using for Switch mode

Place near Pin 20

Place near Pin 3,8,33,46

2

1

C1227
.1U_0402_16V7K

2

1

C1226
.1U_0402_16V7K

2

1

C1225
.1U_0402_16V7K

2

1

C1224
4.7U_0603_6.3V6K

2

1

C1223
.1U_0402_16V7K

High active.
EN threshold voltage min:1.2V typ:1.6V max:2.0V
Current limit threshold 1.5~2.8A

2

1

C1222
1U_0402_6.3V6K

Using for Switch mode
The trace length from Lx to
PIN36 (REGOUT) and from C to Lx
must < 200mils.

From EC

2

1

C1221
.1U_0402_16V7K

2

1

C1220
.1U_0402_16V7K

2

1

C1219
.1U_0402_16V7K

G5243T11U_SOT23-5
Part Number = SA000028Y10

1

1

C1218
.1U_0402_16V7K

<22>

C1217
.1U_0402_16V7K

LAN_PWR_EN

C1216
.1U_0402_16V7K

EN

C1214
1U_0402_6.3V6K

C1215
4.7U_0603_6.3V6K

IN
3

W=60mil
1.4A

1
2
2.2UH_NLC252018T-2R2J-N_5%

2

GND

4

+3V_LAN

+LAN_VDD

300mA

L52

IN

2

W=60mil

IDC=1200mA

W=60mil

1

OUT

5

D

1 0_0805_5%

R1140
10K_0402_5%
2

U68

Power Manahement/Isolation
ISOLATEB
LAN_PME#

RS@
<22>

R1124 1

EC_PME#

2 0_0402_5%

31
39

ISOLATEBPIN
LANWAKEB
PCI-Express

<8>
<8>

CLK_PCIE_LAN
CLK_PCIE_LAN#

<19,22,23,8> PLT_RST_BUF#
<7> LAN_CLKREQ#

C1228,C1230

Place near Pin 25,26

C

C1228 1
C1230 1

<7> PCIE_PRX_DTX_P0
<7> PCIE_PRX_DTX_N0
<7> PCIE_PTX_C_DRX_P0
<7> PCIE_PTX_C_DRX_N0

2 .1U_0402_16V7K
2 .1U_0402_16V7K

CLK_PCIE_LAN
CLK_PCIE_LAN#

23
24

PLT_RST_BUF#
LAN_CLKREQ#

30
29

PCIE_PRX_C_DTX_P0
PCIE_PRX_C_DTX_N0

25
26
21
22

Internal pull high

Card Reader

REFCLK_P
REFCLK_N
PERSTBPIN
CLKREQBPIN

SD_D0/MS_D1
SD_D1
SD_CLK/MS_D0
SD_CMD/MS_D2
SD_D3/MS_D3
SD_D2/MS_CLK
MS_BS/SD_WP#

15
14
16
17
18
19
28

SD_D0
SD_D1
SD_CLK
SD_CMD
SD_D3
SD_D2
SD_WP

42
43

SD_CD#

1
1
1
1
1
1

R1126
R1127
R1128
R1125
R1129
R1130

2
2
2

2
2
2

0_0402_5%
0_0402_5%
10_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

RS@
RS@
RS@
RS@
RS@

SD_D0_R
SD_D1_R
SD_CLK_R
SD_CMD_R
SD_D3_R
SD_D2_R

SD_CLK_R
@EMC@

2

1

C1229

5P_0402_50V8C

Reserve for EMI please close to IC

HSOP
HSON
HSIP
HSIN

SD_CD#
MS_CD#

C

Transceiver Interface
<19>
<19>
<19>
<19>
<19>
<19>
<19>
<19>

LAN_MIDI0+
LAN_MIDI0LAN_MIDI1+
LAN_MIDI1LAN_MIDI2+

LAN_MIDI2LAN_MIDI3+
LAN_MIDI3-

1
2
4
5
6
7
9
10

XTLI
2 R1202 XTLO_R

44
45

MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3

48
11
12

32

HV_GIGA
HV_GIGA
VDD33
VDD33

+3V_LAN

1400mA

1

+3VS

LAN_MIDI0+
LAN_MIDI0LAN_MIDI1+
LAN_MIDI1LAN_MIDI2+
LAN_MIDI2LAN_MIDI3+
LAN_MIDI3-

2

R1131
1K_0402_5%

XTLO

1K_0402_5% 1

ISOLATEB

CKXTAL1
CKXTAL2

33
3
8

VDD10
AVDD10
AVDD10

Clock

2

40mil
R1132
15K_0402_5%

R1133

2

+3V_LAN

+LAN_VDD
LAN_RST

47

SWR mode

1 2.49K_0402_1%

1

10mil

B

13

CARD_3V3

RSET

27

DV33/18
41
38
37
40

LED0
LED1/GPO
LED2
LED_CR

LEDs
49

E_PAD
+3V_LAN

2
@
R1135
10K_0402_5%

2
@
R1197
0_0402_5%

1

2

@

1

2

B

2

Card Reader Connector
JREAD1

RTL8411B-CGT_QFN48_6X6

+CARD_3V3

3
GND

4

1

SD_CMD_R

2
3

Close to Card Reader CONN

1

2

4
5

SD_CLK_R

1

6

2

SD_D0_R

7

SD_D1_R

8

SD_D2_R

9

SD_CD#

10

SD_WP

11

XTLO

GND

2
C1236
15P_0402_50V8J

SD_D3_R

GPO

C1235
.1U_0402_16V7K

2

1

3

C1237
15P_0402_50V8J

Open
Close

1

C1234
4.7U_0603_6.3V6K

1

1

Card Detect

+CARD_3V3

Y10
25MHZ_10PF_7V25000014
XTLI

Write protect
     (Unlock)
Open
Close

+VDD33_18

Place near Pin 27

1

1

Write protect
     (Lock)
Open
Open

800mA

C1233
.1U_0402_16V7K

@ T199
@ T200

20

VDDTX

C1232
4.7U_0603_6.3V6K

@ T198

REG_OUT
VDDREG
ENSWREG
LV_GEN

C1231
.1U_0402_16V7K

GPO

LAN_PHY_EN

Without Card
Card Inserted

Regulator and Reference
36
35
34
46

+REGOUT

<22>

+LAN_VDD

300mA

1

CD/DAT3
CMD
VSS1
VDD
CLK
VSS2
DAT0
DAT1

G1

DAT2

G2

CD

G3

WP

G4

12
13
14
15

TAITW_PSDAT4-11GLBS1NN4H2
CONN@
SP07000ZC00

2

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

LAN RTL8411B-CG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

Z5WAL_Bay Trail M_LA‐B211P

Date:

5

4

3

2

Sheet

Monday, April 07, 2014
1

18

of

39


A

B

C

D

E

LAN Connector
JRJ1

T210

<18>

<18>

LAN_MIDI2LAN_MIDI2+

LAN_MIDI2LAN_MIDI2+

4
5
6

LAN_MIDI1LAN_MIDI1+

LAN_MIDI1LAN_MIDI1+

7
8
9

LAN_MIDI0LAN_MIDI0+

LAN_MIDI0LAN_MIDI0+

10
11
12

<18>
<18>
<18>
<18>

TCT1
TD1+
TD1-

MCT1
MX1+
MX1-

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

TCT4
TD4+
TD4-

MCT4

MX4+
MX4-

24
23
22

RJ45_MIDI3RJ45_MIDI3+

21
20
19

RJ45_MIDI2RJ45_MIDI2+

18
17
16

RJ45_MIDI1RJ45_MIDI1+

15
14
13

RJ45_MIDI0RJ45_MIDI0+

GST5009-E
SP050006B10
1

8
7

RJ45_MIDI1-

6

RJ45_MIDI2-

5

RJ45_MIDI2+

4

RJ45_MIDI1+

3

RJ45_MIDI0-

2

RJ45_MIDI0+

1

PR4-

1

PR4+
PR2PR3PR3+
PR2+
PR1SHLD2
SHLD1

PR1+

10
9
JP40 @EMC@
B88069X9231T203_4P5X3P2-2
2
1

SANTA_130452-0B
DC234005310
CONN@

40mil
1
2
C1239
10P_0402_50V8J

RJ45_GND

2

C1238
.1U_0402_16V7K

40mil

LANGND

1

2

RJ45_MIDI3RJ45_MIDI3+

JP@
JUMP_43X118
JP41
RJ45_GND

1

2

2

60mil

1
1

JUMP_43X118

C441
470P_0402_50V7K
1
EMC@

3

2

1
C458
4.7U_0603_6.3V6K

2

@
C459
.1U_0402_16V7K

1

2

<22>
C460
.1U_0402_16V7K

<7>

WLAN_CLKREQ#

+1.5VS_WLAN
JP9
JUMP_43X39
1
2
2
@ 1
1
@
C461
.1U_0402_16V7K
2

<7> PCIE_PRX_DTX_N1
<7> PCIE_PRX_DTX_P1

<7> PCIE_PTX_C_DRX_N1
<7> PCIE_PTX_C_DRX_P1
+3VS_WLAN

+3VS_WLAN
+3VALW

<22> E51TXD_P80DATA
<22> E51RXD_P80CLK

U9 @

4
1

2

1

W=60mils

VIN
GND

R1079 0_0402_5%
R1080 0_0402_5%

1 RS@
1 RS@

2
2

BT_ON# use RX to work.

1

VOUT

53

WAKE#
3.3V
NC
GND
NC
1.5V
CLKREQ#
NC
GND
NC
REFCLKNC
REFCLK+
NC
GND
NC
NC
GND
NC
NC
GND
PERST#
PERn0
+3.3Vaux
PERp0
GND
GND
+1.5V
GND
SMB_CLK
PETn0

SMB_DATA
PETp0
GND
GND
USB_DNC
USB_D+
NC
GND
NC
LED_WWAN#
NC
LED_WLAN#
NC
LED_WPAN#
NC
+1.5V
NC
GND
NC
+3.3V
GND

GND

2
4
6
8
10
12

14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

3

WL_OFF# <22>
PLT_RST_BUF# <18,22,23,8>

MINI1_SMBCLK R432 1
MINI1_SMBDATAR434 1

@

@

2 0_0402_5%
2 0_0402_5%

EC_SMB_CK2
EC_SMB_DA2
USB20_Hub_N1
USB20_Hub_P1

<13,14,22,9>
<13,14,22,9>
<21>
<21>

54

2
R437
100K_0402_5%

VIN

3
@
EN
C165
1U_0402_6.3V6K G5243AT11U_SOT23-5

WLAN_ON

<22>

2

5

+1.5VS_WLAN

JMINI1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51

WLAN_PME#

<8> CLK_PCIE_WLAN#
<8> CLK_PCIE_WLAN

+1.5VS

2

+3VS_WLAN
R429
4.7K_0402_5%

+3VS_WLAN

JP8 JP@
2

LANGND
JP42
@EMC@
B88069X9231T203_4P5X3P2-2

+3VS_WLAN

For Wireless LAN
+3VS

D47
EMC@
MESC5V02BD03_SOT23-3

Place close to TCT pin

2

LAN_MIDI3LAN_MIDI3+

3

LAN_MIDI3LAN_MIDI3+

2

<18>
<18>

LAN_TERMAL1
2
3

1
R1136

75_0402_1%
2
1
R1137
75_0402_1%
2
1
R1138
75_0402_1%
2
1
R1139
75_0402_1%

1

ACES_50709-0524W-P01
CONN@
DC04000C400

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

LAN/WLAN/BT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

E

19

of

Rev
1.0
39


A

B

C

D

E

SATA Re-Driver HDD2 Conn. Reserve
+3VS

2

1

SATA_PTX_DRX_P0
SATA_PTX_DRX_N0

RD@
RD@

C1248 2
C1249 2

1 SATA_PTX_C_DRX_P0_1 0.01U_0402_16V7K
1 SATA_PTX_C_DRX_N0_1 0.01U_0402_16V7K

1
2

SATA_PRX_DTX_P0
SATA_PRX_DTX_N0

RD@
RD@

C1250 2
C1251 2

1 SATA_PRX_C_DTX_P0_1 0.01U_0402_16V7K
1 SATA_PRX_C_DTX_N0_1 0.01U_0402_16V7K

5
4

R1190
2

+3VS

APE1
BPE1

19
17

TEST

18
3
13
21

1
2

2

4.7K_0402_5%
@
R1192
0_0402_5%
8520@

B_OUTp
B_OUTn
A_PRE1
B_PRE1
TEST
GND
GND
EPAD

2
VDD
VDD
NC
NC
A_PRE0
B_PRE0
A_OUTp
A_OUTn
B_INp
B_INn

10
20
6
16

1

2

SATA HDD2 Cable Conn.
CL 4.0 mm

1 R1184 2 8527@
4.99K_0402_1%

9
8

APE0
BPE0

15
14

RDSATA_PTX_DRX_P0
RDSATA_PTX_DRX_N0

11
12

RDSATA_PRX_DTX_P0
RDSATA_PRX_DTX_N0

RDSATA_PTX_DRX_P0
RDSATA_PTX_DRX_N0

C1244 1
C1242 1

2 RD@
2 RD@

0.01U_0402_16V7K RDSATA_PTX_C_DRX_P0
0.01U_0402_16V7K RDSATA_PTX_C_DRX_N0

RDSATA_PRX_DTX_N0
RDSATA_PRX_DTX_P0

C1243 1
C1245 1

2 RD@
2 RD@

0.01U_0402_16V7K RDSATA_PRX_C_DTX_N0
0.01U_0402_16V7K RDSATA_PRX_C_DTX_P0

+5VS_HDD

PS8520CTQFN20GTR2-A_TQFN20_4X4
RD@

+3VS

2

R1181 1

RD@ 2 4.7K_0402_5%

APE0

R1187 1

@

2 4.7K_0402_5%

APE0

R1182 1

RD@ 2 4.7K_0402_5%

BPE0

R1188 1

@

2 4.7K_0402_5%

BPE0

R1183 1

@

2 4.7K_0402_5%

APE1

R1189 1

RD@ 2 4.7K_0402_5%

APE1

R1185 1

@

2 4.7K_0402_5%

BPE1

R1191 1

RD@ 2 4.7K_0402_5%

BPE1

R1186 1

@

2 4.7K_0402_5%

TEST

R1194 1

RD@ 2 4.7K_0402_5%

TEST

1

JHDD2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21
22
23
24

Check BOM structure

1

1

R1193
4.7K_0402_5%
8527@

A_INp
A_INn

1

RD@ C1247
0.1U_0402_16V7K

R1180
4.7K_0402_5%
RD@
U69
7
EN

RD@ C1246
0.01U_0402_16V7K

1

+3VS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
G1
G2
G3

G4
ACES_50406-02071-001
CONN@
SP010016L00
2

FAN1 Conn
SATA HDD1 Conn.

+5VS

C632
4.7U_0603_6.3V6K
1
2

SATA ODD Conn.

JHDD1

U31

SATA_PRX_DTX_N0
SATA_PRX_DTX_P0

C391 1
C394 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
+3VS

+5VS

100mils

2

1

2

C397
.1U_0402_16V7K

@

1

C161
1U_0402_6.3V6K

2

C420
10U_0603_6.3V6M

1

+VCC_FAN1
<7> SATA_PTX_DRX_P1
<7> SATA_PTX_DRX_N1
<7>
<7>

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

SATA_PRX_DTX_N1
SATA_PRX_DTX_P1

C401 1
C402 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1

C403 1
C405 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1

1
2
3
4
5
6
7

<22>

GND

A+
AGND
BB+
GND

EN_DFAN1

EN
VIN
VOUT
VSET

8
7
6
5

GND
GND
GND
GND

3

APE8875M_SO8

 SA000050J00

+5VS
R1154 1 RS@

2 0_0805_5%
1

2
GND
GND
GND
GND

23
24
25
26

80mils
1

2

C407
.1U_0402_16V7K

+5VS_HDD

2 0_0805_5% +5VS_HDD

1
2
3

4

JODD1

C404
10U_0603_6.3V6M

R1155 1 RS@

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

GND
A+
AGND
BB+
GND

+5VS_ODD
ODD_MD
T185
@

8
9
10
11
12
13

DP
+5V
+5V
MD
GND
GND

+3VS

GND
GND

C629
4.7U_0603_6.3V6K
1
2

1

<7>
<7>

C392 1
C393 1

14
15

R516
10K_0402_5%

40mil

SANTA_201902-1_13P
CONN@
SP01001RS00

2

3

<7> SATA_PTX_DRX_P0
<7> SATA_PTX_DRX_N0

1
2
3

4
5
6
7

<22>

JFAN1
1
2
3

+VCC_FAN1

FAN_SPEED1
1

CCM_C127043HR022M27FZR_22P
CONN@
DC010009X00

2

EMC@
C630
.1U_0402_16V7K

1
2 GND
3 GND

4
5

ACES_88231-03041
CONN@
SP020020710

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

HDD/ODD/FAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

E

20

of

Rev
1.0
39

A

B

<9>

1

<9>

PCH_USB3_TX0_P
PCH_USB3_TX0_N

2
C484

1
PCH_USB3_TX0_P_C
.1U_0402_16V7K

2

2
C482

1
PCH_USB3_TX0_N_C
.1U_0402_16V7K

3

C

L24 EMC@
CMMI21T-900Y-N_4P
1
2
1
3

4

4

D

+5VALW

For ESD request
U3TXDP0
D15
U3TXDN0

E

+USB3_VCCA

U3RXDN0

1 1

109

U3RXDN0

U3RXDP0

2 2

98

U3RXDP0

1
2
3
4

USB_PWR_EN#

SM070003K00

W=60mils

U25

@EMC@
2 C483
.1U_0402_16V7K1

@EMC@

GND
IN
IN
EN/ENB

OUT
OUT
OUT
OCB

8
7
6
5

R454 1

@

2 0_0402_5%

USB_OC0#

1

<9>

SY6288D10CAC_MSOP8

<9>

PCH_USB3_RX0_P

<9>

PCH_USB3_RX0_N

2

PCH_USB3_RX0_P

L25 EMC@
CMMI21T-900Y-N_4P
1
2
1

3

PCH_USB3_RX0_N

3

4

4

U3TXDN0

4 4

77

U3TXDN0

U3TXDP0

5 5

66

U3TXDP0

U3RXDP0

+USB3_VCCA

3 3
8

U3RXDN0

SM070003K00

W=100mils

L05ESDL5V0NA-4 SLP2510P8

<9>

USB20_P0

<9>

USB20_N0

RS@ 2 0_0402_5%

2

L26 @EMC@
DLW21HN900HQ2L_4P
2
1
2
1
3

3

4

1

1

USB3.0 Conn.

JUSB1
1
2
3
4
5
6
7
8
9

USB20_P0_L
USB20_N0_L
USB20_P0_L

4

USB20_N0_L
U3RXDN0
U3RXDP0

SM070003Y00
R461 1

2

C994 @EMC@
.1U_0402_16V7K

R458 1

2

C487 @EMC@
1000P_0402_50V7K

+

C486
150U_6.3V_M_D2

1

RS@ 2 0_0402_5%

U3TXDN0
U3TXDP0

VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+

10
11
12
13

GND
GND
GND
GND

ACON_TARAC-9V1391
CONN@
DC23300AG00

2

+3VALW
+3V_HUB

1
C280

2
.1U_0402_16V7K

1
C283

2
.1U_0402_16V7K

1
C284

2

.1U_0402_16V7K

1

C279 close to U72 pin5
C280 close to U72 pin9
C283 close to U72 pin14
C284 close to U72 pin21

2

1

2

C281
.1U_0402_16V7K

2
.1U_0402_16V7K

+3V_HUB
R259
0_0603_5%
1 RS@
2

C282
10U_0603_6.3V6M

1
C279

2

USB/B Conn.
(USB Port 1, Port2)

+3V_HUB

3

U72
5
9
14
21
27
28

+3V_HUB

2
PSELF
100K_0402_5%

1
R1134
1
R1141

2

1
R264
1
R265

2
OVCUR2#
10K_0402_5%
2
OVCUR3#
10K_0402_5%

1
R262

2
PGANG
100K_0402_5%

HUB_DM4
1K_0402_5%
2
HUB_DP4
1K_0402_5%

R263
10K_0402_5%

Port4 disable.

2

1
R261

1

+3V_HUB

RESET#
2

Port2,3 is removable.

18
26

1

C285
1U_0402_6.3V6K

17

HUB_XIN
HUB_XOUT

10
11

PSELF
PGANG

22
23
29

AVDD
AVDD
AVDD
DVDD
V5
V33

DM0
DP0
DM1
DP1
DM2
DP2

TEST/SCL
PWREN1#/SDA

DM3
DP3

RESET#
DM4
DP4

X1
X2
PSELF
PGANG
GND

OVCUR1#/SMC
OVCUR2#/SMD
OVCUR3#
OVCUR4#
RREF

1
2

USB20_N1
USB20_P1

3
4

USB20_Hub_N1
USB20_Hub_P1

6
7

USB20_Hub_N2
USB20_Hub_P2

12
13

USB20_Hub_N3
USB20_Hub_P3

15
16

HUB_DM4
HUB_DP4

25
24
20
19

OVCUR2#
OVCUR3#

8

<9>
<9>

RREF

2
R260

3

+5VALW
JUSB2
<19>
<19>

1
2
3
4
5
6
7
8
9
10
11
12
13
14

To BT
<22>

USB_PWR_EN#

USB_PWR_EN#
USB20_Hub_N2
USB20_Hub_P2
USB20_Hub_N3
USB20_Hub_P3

Port4 disable.
Port2,3 is removable.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
ACES_88514-01201-071
CONN@
SP01001BF00

1
680_0402_1%

GL850G-OHY31_QFN28_5X5

SA000066310, S IC GL850G‐OHY32 QFN 28P USB2.0 HUB
4

4

Y9
HUB_XIN
C287
20P_0402_50V8

1

4

2

C286
20P_0402_50V8
2 HUB_XOUT
3

1

2

12MHZ_18PF_7V12000001

1

Security Classification
Issued Date

Compal Electronics, Inc.

Compal Secret Data
Title

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

USB Conn & Hub GL850G

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

E

21

of

Rev
1.0
39


B

C

D

E

R488
R492
R494

EC_RST#

<8> EC_SCI#
<19> WLAN_ON

2.2K_0804_8P4R_5%

+1.8VALW_EC

2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

1 9022@ 2 10K_0402_5%
1 9022@ 2 10K_0402_5%
1 9022@ 2 10K_0402_5%

EC_SMI#
EC_SCI#
EC_LID_OUT#

+3VALW_EC

R489
R493
R495

1 9012@ 2 10K_0402_5%

1 9012@ 2 10K_0402_5%
1 9012@ 2 10K_0402_5%

EC_SMI#
EC_SCI#
EC_LID_OUT#

<23>
<23>

KSI[0..7]

KSI[0..7]

KSO[0..17]

KSO[0..17]

@EMC@
2 0.01U_0402_16V7K PLT_RST_BUF#
C511 1

ESD request
R485 2

1 100K_0402_5% PMC_CORE_PWROK

Charger and BATT
To SOC

<27,28>
<27,28>
<13,14,19,9>
<13,14,19,9>

<8>
3

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SLP_S3#

<8> EC_SMI#
<15> TS_RST#
<15> TS_EN
<19> WL_OFF#
<29,31,32> SPOK
<20> FAN_SPEED1
<19> E51TXD_P80DATA
<19> E51RXD_P80CLK
<8> PMC_CORE_PWROK
<23> PWR_SUSP_LED#

<8> PBTN_OUT#
<8> EC_SLP_S4#

KSI0

KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

55
56
57
58

59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
77
78
79
80

6
14
15

16
17
18
19
25
28
29
30
31
32
34
36

122
123

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

Rb

1

@
C517
.1U_0402_16V7K

2

2

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

SPI Flash ROM

2

2
R478
R479

1
1

2
2

4.7K_0402_5%
4.7K_0402_5%

BEEP#

BEEP#

<24>

EC_MUTE#

R481

1

2

10K_0402_5%

@

EC_CLR_CMOS

63
64
65
66
75
76

C510 2
BATT_TEMP
VCIN1_BATT_DROP
ADP_I
AD_BID0
WLAN_PME#
EC_PME#

68
70
71
72

LAN_PWR_EN
EN_DFAN1
TP_EN
KBL_EN#

83
84
85
86
87
88

EC_MUTE#
USB_PWR_EN#
EC_I2C_TPCLK
EC_I2C_TPDAT
TP_CLK
TP_DATA

97
98
99
109

VCIN0_PH

119
120
126
128

1 100P_0402_50V8J ECAGND
VCIN1_BATT_DROP
ADP_I <27,28>

BATT_TEMP <27>
<27>

Reserve EC_CLR_CMOS for clear CMOS

WLAN_PME# <19>
EC_PME# <18>

CLR_CMOS#

LAN_PWR_EN <18>
EN_DFAN1 <20>
TP_EN <23>
KBL_EN# <23>

GPIO
Bus

GPIO

ENBKL/AD6/GPIO40
PECI_KB930/AD7/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07

V18R

73
74
89
90
91
92
93
95
121
127

ENBKL <6>
TP_PWR_EN <23>
TXE_DBG <7>
VCIN0_PH <27>

EC_MISO
EC_MOSI
EC_SPICLK
EC_SPICS#

2
G

R483
10K_0402_5%
@

EC_MUTE# <24>
USB_PWR_EN# <21>
EC_I2C_TPCLK <23>
EC_I2C_TPDAT <23>
TP_CLK <23>
TP_DATA <23>

ENBKL

H_PROCHOT#_EC

EC_MISO <8>
EC_MOSI <8>
EC_SPICLK <8>
EC_SPICS# <8>

<33>

R1169 1

TP_INT#_EC

BATT_BLUE_LED#
PWR_LED
BATT_AMB_LED#
SYSON
VR_ON

2

R482 2 RS@

VR_HOT#

1 0_0402_5%

H_PROCHOT#

EC_RSMRST#
EC_LID_OUT#
VCIN1_PROCHOT
H_PROCHOT#_EC
MAINPWON
EC_BKOFF#
LAN_PHY_EN

110
112
114
115
116
117
118

EC_ACIN
EC_ON
ON/OFFBTN#
LID_SW#
SUSP#
VGATE

124

+V18R

<7>

D
2
S

<23>

BATT_BLUE_LED#

Q50
2N7002K_SOT23-3
9012@

<23>

PWR_LED <23>
BATT_AMB_LED# <23>
SYSON <30>
VR_ON <33>

100
101
102
103

104
105
106
107
108

Q51
2N7002K_SOT23-3
@

RS@ 2 0_0402_5%

Latest design guide suggest change to
74LVC1G06.

EC_RSMRST# <8>
EC_LID_OUT# <8>
VCIN1_PROCHOT <27>
H_PROCHOT#_EC <27>
MAINPWON <27,29>
EC_BKOFF# <15>
LAN_PHY_EN <18>

R509 2 RS@
EC_ACIN

EC_ON <29>
ON/OFFBTN# <23>
LID_SW# <23>
SUSP# <10,25,30,31,32>

VGATE <33>
R1092 1 RS@

1
C515
4.7U_0603_6.3V6K
9012@

C512

1 0_0402_5%

ACIN

3

<28,8>

EMC@
2
1 100P_0402_50V8J

+3VALW_EC
+1.8VALW_EC

2 0_0603_5%

For 9022 +V18R, +EC_VCCLPC can be
changed to 1.8V if supports 1.8V I/F

@
R696
10K_0402_5%
VCIN0_PH
VCIN1_PROCHOT

20mil

@
R697
10K_0402_5%

Revision

EVT

0.2

1

DVT

0.3

2

PVT

0.5

3

*Pre‐MP

1.0

4

EC_RSMRST#

U28
9022@

BID0

EMC@
2 .1U_0402_16V7K
C1156 1
4

For ESD request

S IC KB9022QC LQFP 128P
SA000075S20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

EC ENE KB9012/KB9022

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

S

G
TP_INT#_EC

2

<8>

D
EC_CLR_CMOS

H_PROCHOT#_EC

11
24
35
94
113

1

Phase

1
R506
27K_0402_5%

TP_CLK
TP_DATA

2
ECAGND 1
L32
BLM15AG121SN1D_L0402_2P

Analog Board ID definition,
Please see page 3.

AD_BID0

47K_0402_5%

+3VS

21
23
26
27

SPI Device Interface

XCLKI/GPIO5D
XCLKO/GPIO5E

Board ID

2

Ra

EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

+3VALW_EC

4

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

PS2 Interface

KB9012QF-A4_LQFP128_14X14
Part Number = SA00004OB30
9012@

R503
100K_0402_5%

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13

BATT_TEMP/AD0/GPIO38
AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
IMON/AD5/GPIO43

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36

KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

2

67

AD

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E

GPIO1D

1

+3V_PTP

PWM Output

GND/GND
GND/GND
GND/GND
GND/GND
GND0

+3VS

8
7
6
5

R476

1

<9> LPC_CLK_EC
<18,19,23,8> PLT_RST_BUF#

RP12
1

2
3
4

12
13
37
20
38

LID_SW#

1

+3VALW_EC

1

+3VALW_EC

3

EC_SLP_S3#

+VCC_LPC

2

2 100K_0402_5% EC_PME#

TPM@

1

@

R496 1 TPM@ 2 10K_0402_5%

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

RS@ 1 0_0805_5%

R1091
0_0603_5%

<27>

2

R484 1

1

2
3
4
5
7
8
10

<8> EC_KBRST#
<23,8> EC_SERIRQ
<23,9> LPC_FRAME#
<23,9> LPC_AD3
<23,9> LPC_AD2
<23,9> LPC_AD1
<23,9> LPC_AD0

R237 2

NTPM@

1

9012@

+1.8VALW_EC

2

.1U_0402_16V7K

+3VALW_EC

C508
.1U_0402_16V7K
ECAGND

AGND/AGND

C509

1

2

EC_VDD/AVCC

U28

2

1

+VCC_LPC

1

2

69

EC_RST#

2

2

R1090
0_0603_5%
+1.8VALW

1

9
22
33
96
111
125

2

1

C507 @EMC@
1000P_0402_50V7K

2

1

C506 @EMC@
1000P_0402_50V7K

2

1

C505
@
.1U_0402_16V7K

R480 2 9012@ 1 47K_0402_5%

1

C504
@
.1U_0402_16V7K

+3VALW_EC

C503
.1U_0402_16V7K

1

C502
.1U_0402_16V7K

R236

0_0805_5%

+EC_VCCA

L31
BLM15AG121SN1D_L0402_2P
1
2 +EC_VCCA

RS@ 1

1

+3VALW_EC
2

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

+3VLP

1

+3VALW_EC

1

+1.8VALW_EC

3

A

B

C

D

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

E

22

of

Rev
1.0
39


A

B

C

+3V_PTP
U10
VIN

KSI[0..7]

1
1

1

@

@

@

2 0_0402_5%

+3VALW

R1171 1

@

2 0_0402_5%

+3VS

8
7
6
5
4
3
2
1

C663 1
TP_CLK
TP_DATA
TP_SDATA
TP_SCLK
TP_INT#_R
TP_EN

2 .1U_0402_16V7K

<9>

I2C2_SDA_TP

<9>

I2C2_SCL_TP

TP_CLK <22>
TP_DATA <22>

TP_EN

<22>

EC_I2C_TPDAT

<22>

EC_I2C_TPCLK

R1164 1

RS@ 2 0_0402_5%

TP_SDATA

R1165 1

RS@ 2 0_0402_5%

TP_SCLK

R1167 1

@

2 0_0402_5%

R1168 1

@

2 0_0402_5%

FD3

FD4

@

R1163 1

RS@ 2 0_0402_5%

H23
H_3P0X3P5N

@

1

@

1

@

@

@

Stand off for BATT/B.

2

TP_INT#

@EMC@
C551
100P_0402_50V8J

3

<22>

BATT_BLUE_LED#

BATT_BLUE_LED#

1

1

1

1

2

2

<22>

@EMC@
C553
100P_0402_50V8J

BATT_AMB_LED#

BATT_AMB_LED#

3

B
A

2

1
R699

2
200_0402_1%

4

1
R698

2
390_0402_5%

2

1
R700

2
200_0402_1%

4

1
R701

2
390_0402_5%

2

LTST-C295TBKF-CA_AMBER-BLUE
LED7

TP_INT#_R

D

S

TP_INT#

+3VALW

LED6

G

<8>

1

@

1
R1166
2.2K_0402_5%

@

FIDUCIAL_C40M80

TP_INT#_R

TP_CLK
TP_DATA

<22>

@

1

H21
H_3P2

LED

TP_INT#_EC

<22>

KSO[0..17]

FIDUCIAL_C40M80

FIDUCIAL_C40M80

<22>
<22>

H12
H_3P2

+1.8VS

KSI[0..7]

KSO[0..17]
2

1

1

@

@

FIDUCIAL_C40M80

1

R1170 1

CVILU_CF31081D0R4-10-NH
CONN@

E-T_6905-E26N-01R
CONN@
SP01000IJ00

@

H22
H_3P0N

JTP1

27
28

@

1

TP module Conn.

G1
G2

@

H13
H14 H15
H_4P0 H_4P0 H_4P0

+3V_PTP

8
7
6
5
4
3
2
1

@

FD2
@

1

2
2.2K_0402_5%
2
2.2K_0402_5%
1
10K_0402_5%

1

TP_SCLK

TP_PWR_EN

1
R1156
1
R1157
2
R633

1

TP_SDATA

TP_INT#_R

G2
G1

FD1

G5243AT11U_SOT23-5

2
<22>

9
10

1

+3V_PTP

1

2

3

EN

1

1
C141
1U_0402_6.3V6K

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26

C368
4.7U_0603_6.3V6K

2

1

VIN

1

JKB1

H9
H10
H11 H8
H17
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

1

2

GND

4
1
2

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

H3
H4
H_3P0 H_3P0

W=20mils

1

VOUT

5

KB Conn.
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3

KSI4
KSI5
KSI6
KSI7

E

1

+3VALW

D

PWR_LED#

1

PWR_SUSP_LED#

3

B

Q77
MESS138W-G_SOT323-3
<22>

PWR_SUSP_LED#

A

LTST-C295TBKF-CA_AMBER-BLUE

KB BackLight Conn. Reserve
BL@
Q44
DMG2301U-7_SOT23-3

+5VS

JBL1

KBL_EN_R

1
<22>

RS@

1

KBL_EN#

2
2

R592
0_0402_5%

+3VALW

+3VALW_TPM

2

2

2

4

R534
100K_0402_5%
1
ON/OFFBTN#

5
6

1

1
2

1
LPC_CLKRUN#

2

1

2

C406 TPM@
.1U_0402_16V7K

1

1

@

2 R1172

EEh ‐ EFh

* 1

7Eh ‐ 7Fh

1
2
6
9
15
26
23
20
17

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

Internal PU

SELECTION

0

TPM_BADD

LPC_CLKRUN#

<22,9>
<22,9>
<22,9>
<22,9>

Internal PU
<9> LPC_CLK_TPM
<22,9> LPC_FRAME#
<18,19,22,8> PLT_RST_BUF#
<22,8> EC_SERIRQ

28
21
22
16

27
7

LPC_CLK_TPM

near Pin10,19,24

Issued Date

GPIO0/XOR_OUT
GPIO1
GPIO2/GPX
GPIO3/BADD
GPIO4/CLKRUN#
LAD0/MISO
LAD1/MOSI
LAD2/SPI_IRQ#
LAD3
LPCPD#
LCLK/SCLK
LRFAME#/SCS#
LRSET#/SPI_RST#
SERIRQ
PP

VSB
VDD
VDD
VDD
TEST

NC
NC
NC
NC

GND
GND
GND
GND

@EMC@
@EMC@
2 33_0402_5% C175 1
2 22P_0402_50V8J
R148 1

8

3
12
13
14

4
11
18
25

Compal Electronics, Inc.

Compal Secret Data
2013/04/12

2014/04/12

Deciphered Date

Title

KB/TP/LED/TPM/Screw Hole

Date:

B

5
10
19
24

NPCT650AA0WX_TSSOP28
SA00007IO00

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

+3VS_TPM

TPM@

4

Security Classification

5
6

0_0402_5%

near Pin5

C400 TPM@
.1U_0402_16V7K

2

C399 TPM@
.1U_0402_16V7K

C422 TPM@
10U_0603_6.3V6M

4

1

Q17
2N7002K_SOT23-3

+3VALW_TPM
U70

<9>

2 R1204

2
SW2 DBG@
TJE-532QR5_6P
3

S

3

+3VS_TPM

BADD

1

2

2

TPM@
0_0603_5%

G
R452
100K_0402_5%

R517 TPM@
10K_0402_5%

+3VS_TPM

<22>

4

1

1

+3VS
ON/OFFBTN#

2

2

PWR_LED

@

2

1

EMC@
2 .1U_0402_16V7K
C408 1

C398 TPM@
.1U_0402_16V7K

+3VLP

SW1 @
TJE-532QR5_6P
1
3

1

<22>

2 R1203
C421 TPM@
10U_0603_6.3V6M

ON/OFF BTN
Test only

1

@

TPM Reserve

TPM@
0_0603_5%

PWR_LED#
D

ACES_50504-0040N-001
SP01000Z300
CONN@

<22>

ACES_51524-0060N-001
SP010014M10
CONN@

6
5

3

2

2 R451

G2
G1

1

LID_SW#
PWR_LED#
ON/OFFBTN#

BL@
1
100K_0402_5%

4
3
2
1

C524
.1U_0402_16V7K

3

+3VALW
+3VLP
LID_SW#

C525
.1U_0402_16V7K

7
8

1
2
3
4
5
6

4
3
2
1

1+5VS_BL

G

+5VALW

JPWR1
1
2
3
4
G1 5
G2 6

D

S
3

PWR/B Conn.

C

D

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

E

23

of

Rev
1.0
39


C

D

+5VS

+AVDD1_HDA

1

20mil

2

CPVREF

20

1 C1202

MIC_CAP

19

VREF
JDREF
CPVEE

MIC-CAP

7
39
27

C1198 2

1 10U_0603_6.3V6M

GND

LDO2_CAP

C1200 2

1 10U_0603_6.3V6M

GNDA

C1201 2

LDO1_CAP

28

1

1 10U_0603_6.3V6M
2 100K_0402_5%

CODEC_VREF

15
34

20K_0402_1% 1

JDREF
CPVEE

25
38

2

2 R1106

2

GND

1

Q75B

3

HP_LEFT R1109 1

2 0_0603_5%

HPOUT_L_1

R1110 1

2 60.4_0603_1%

HP_RIGHT R1112 1

2 0_0603_5%

HPOUT_R_1

R1113 1

2 60.4_0603_1%

1

2

3

2
1

2
1

2
1

2

L57 EMC@
1
2
BLM15PX330SN1D_2P
1
2
BLM15PX330SN1D_2P
L58 EMC@

R1108
2.2K_0402_5%
SLEEVE
3

RING2

GND

Headphone Jack

+MICBIAS

LINE1-L

C1209 1

2 4.7U_0603_6.3V6K

LINE1-R

C1210 1

2 4.7U_0603_6.3V6K

C1211
@EMC@
330P_0402_50V7K

D44
2

R1120 2

1 4.7K_0402_5%

2

1

RING2_L
HPOUT_L_2

3
1

HP_PLUG#

5
6

HPOUT_R_2

2

SLEEVE_L

4
7

2

C1212
@EMC@
330P_0402_50V7K
1

SINGA_2SJ3080-001111F
DC23000B300
CONN@

GNDA

4

1

GNDA

3

R1121 2

1 4.7K_0402_5%
GNDA

BAT54A-7-F_SOT23-3

GNDA

To solve the background noise while combo jack
connecting to an active
speaker and system entry into S3/S4/S5 without analog
power
GNDA

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

HD Audio Codec_ALC283-CG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

1

2

3
1

2

SLEEVE_L
RING2_L

1
6

1 10K_0402_5%

Q75A

4

2
1

1

2

1

GNDA

2

R1122 2

G

2

S

GND

1 10K_0402_5%

D

GNDA

HDA_RST_AUDIO#

R1119 2

5

G

J5
JUMP_43X39
1
2
2
@ 1
J7
JUMP_43X39
1
2
2
@ 1

1

Place next pin27

RING2

S

J4
JUMP_43X39
1
2
2
@ 1
J6
JUMP_43X39
1
2
2
@ 1

<7>

D48
MESC5V02BD03_SOT23-3
@EMC@

JHP1

D

J3
JUMP_43X39
1
2
2

@ 1

1

GNDA

C1206
2.2U_0402_6.3V6M

DMN66D0LDW-7_SOT363-6

GND

J2
JUMP_43X39
1
2
2
@ 1

EC_MUTE#

DMN66D0LDW-7_SOT363-6

4

<22>

3

R1107
2.2K_0402_5%

GND

@

GNDA

DMIC_CLK

Main

+3VLP

R1118
100K_0402_5%

2

CLK

ENHANCE GND

DMIC_DATA

4

C2142 EMC@
680P_0402_50V7K

1

@

C2143 EMC@
680P_0402_50V7K

R1114
47K_0402_5%
2
1

1

CS

5

S MIC ST MP45DT02TR

HPOUT_L_2
HPOUT_R_2

GNDA

GND

R1115
4.7K_0402_5%

SOC_SPKR

2

2

@
DATA

+MIC2_VREFO

GNDA

C1207
1U_0402_6.3V6K
1
2 MONO_IN
C1208 @EMC@
100P_0402_50V8J

<9>

BEEP#

<7>

10mil

Close codec

GND

<22>

Slave

LDO3_CAP
29

ALC283-CG_MQFN48_6X6

BEEP#_R

3

1

2 R1199 1
0_0402_5%
2DMIC@

D46
EMC@
AZ5123-02S.R7G_SOT23-3

AVSS1
AVSS2

DMIC_CLK

S MIC ST MP45DT02TR

HDA_SDOUT_AUDIO
HDA_SDIN0 <7>

1
DVSS
Thermal PAD

4

+MIC2_VREFO

R1104

CPVREF

CLK

VDD

1

LDO3-CAP
LDO2-CAP
LDO1-CAP

DATA

2

DMIC_DATA_S

16

CPVDD

4
49

R1111
47K_0402_5%
2
1
@

1

40
AVDD2

46

26
AVDD1

PVDD2

41

PVDD1

MIC2-VREFO
CBP
CBN

48

5

ENHANCE GND

GND

MIC2
6

@

D45
@EMC@
MESC5V02BD03_SOT23-3

1 R1123

9

SENSE A
SENSE B

1 @EMC@2
1
2 C1197 @EMC@
22P_0402_50V8J
R1100
0_0402_5%
HDA_SDOUT_AUDIO
1
2
HDA_SDIN0_AUDIO
R1102
33_0402_5%

5
8

CS

HDA_SYNC_AUDIO
<7>
HDA_BITCLK_AUDIO <7>

C1205
@
10U_0603_6.3V6M

@

10U_0603_6.3V6M 2

HDA_SYNC_AUDIO
HDA_BITCLK_AUDIO

VDD

1

C1204
2.2U_0402_6.3V6M

GNDA

100K_0402_5% 2

10
6

6

C1203
0.1U_0402_16V4Z

+3VS
3

MONO-OUT

36

+3VS_DVDD

SDATA-OUT
SDATA-IN
SPDIF-OUT/GPIO2

37
35

CBP
CBN

C1199
2.2U_0402_6.3V6M

HP_LEFT
HP_RIGHT

MIC1

1

1

ALC283-CG

PCBEEP

13
14

SENSE_A

32
33

+3VS

Digital MIC

G1
G2

2

39.2K_0402_1%

SPKR+
SPKR-

2

10mil

12

SPKLSPKL+

45
44

1
2

ACES_88266-02001
SP020008Y00
CONN@

GND

3

1

MONO_IN

SYNC
BCLK

GPIO0/DMIC-DATA
GPIO1/DMIC-CLK
PDB
RESETB

3
4

R1200 1DMIC@
0_0402_5%

2

47
11

+3VS

43
42

2
HPOUT-L(PORT-I-L)
HPOUT-R(PORT-I-R)

LINE1-VREFO-L
LINE1-VREFO-R

2
3

EC_MUTE#
HDA_RST_AUDIO#

SPK-OUT-R+
SPK-OUT-R-

MIC2-L(PORT-F-L) /RING2
MIC2-R(PORT-F-R) /SLEEVE

31
30

C1252
@EMC@
220P_0402_50V7K

C2140
0.1U_0402_16V4Z

R1103

1

2
17
18

+MICBIAS
+MICBIAS2

SPK-OUT-LSPK-OUT-L+

LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R)

JMIC1
1
2

INT_MIC_R_1

GNDA

LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R)

24
23

2

15mil

@EMC@
2 0_0603_5%

R1198 1DMIC@
0_0402_5%

HP_PLUG#

1
DVDD

22
21

LINE1-L
LINE1-R
2
LINE2_C_L

4.7U_0603_6.3V6K
2
LINE2_C_R
4.7U_0603_6.3V6K
RING2
SLEEVE

DVDD-IO

GND

R1196 1
1

Place near Pin40
U66

DMIC_DATA
DMIC_CLK

Close codec

15mil
INT_MIC_R

D43 @EMC@
MESC5V02BD03_SOT23-3

+MICBIAS
+MICBIAS2

Int. MIC Reserve

2

Combo MIC 40mil

1

@ R1195
2.2K_0402_5%

+1.5VS

3

1
@
1
@

GNDA

2 0_0603_5%

1

GNDA

2

1 INT_MIC C770
@
R726
1K_0402_5%
2
C62 1
C769
@EMC@ 1000P_0402_50V7K

C1196
0.1U_0402_16V4Z

C1195
10U_0603_6.3V6M

2

Place near Pin 1

INT_MIC_R

1

2

Internal MIC Reserve
2

R1099 1 RS@

20mil

2

GND

5
6

ACES_88266-04001
GND
SP02000K200
CONN@

GNDA

1

GND

1

GND

G1
G2

+MICBIAS2

+1.5VS_VDDA

+3VS_DVDD

2 0_0603_5%
1

+VDDA

C1194
10U_0603_6.3V6M

+3VS

Place near Pin26

C1193
0.1U_0402_16V4Z

Place near Pin9

2

@

2 0_0603_5%

C1191
10U_0603_6.3V6M

2

C1192
0.1U_0402_16V4Z

C2141
1U_0402_6.3V6K

1

1

1

C1190
0.1U_0402_16V4Z

2
2

R1098 1 RS@

20mil

2 0_0603_5%

C1189
0.1U_0402_16V4Z

+1.5VS

1

+1.5VS_DVDDIO

GND
R1201 1 RS@

R1093 1 RS@

2

GND

1
2
3
4

2

Place near Pin46

2

Place near Pin41

1
2
3
4

SPK_R+
SPK_RSPK_L+
SPK_L-

1

GND

JSPK1

40mil

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
2

(output = 300 mA)

2
2
2
2

RS@
RS@
RS@
RS@

1

2

4.75V

1
1
1
1

R1094
R1095
R1096
R1097

D42 @EMC@
MESC5V02BD03_SOT23-3

@

SPKR+
SPKRSPKL+
SPKL-

MESC5V02BD03_SOT23-3
D41 @EMC@

2

1

40mil

2

JUMP_43X118
@

C1185
0.1U_0402_16V4Z
2
@EMC@

C1188
0.1U_0402_16V4Z

2

C1187
0.1U_0402_16V4Z

C1186
10U_0603_6.3V6M

1

1

1

1
L51 2
HCB2012KF-221T30_0805
1

+VDDA

Int. Speaker Conn.

+VDDA
J1

40mil

+PVDD_HDA

40mil

2

HD Audio Codec
SM01000EJ00 3000ma 220ohm@100mhz DCR 0.04

E

3

B

3

A

B

C

D

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

E

24

of

39

Rev
1.0


A

B

C

VIH=1.2~5.5V
3.3V@100k/0.1uF=3.538ms
3.3V@120k/0.1uF=4.272ms

1

U11

0701 update

2
C980
.1U_0402_16V7K
1
2
R926
120K_0402_5%
1
C979
.1U_0402_16V7K

1
2

+3VALW

R927
100K_0402_5%
2
1

SUSP#

D

3VS_ON
1

5VS_ON

5
6
7

+5VALW

2

3
4

+5VALW

Rise Time:
3.3V@330pF = 889.68us
5.0V@330pF = 1348us

JP36JP@

VIN1
VIN1

VOUT1
VOUT1

ON1

CT1

VBIAS

GND

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2
GPAD

14
13

12

+3VS_OUT

+3VS

2

C976
1 330P_0402_50V7K

2

1

E

1

JUMP_43X118

11
10

330P_0402_50V7K
C967
+5VS_OUT

9
8

15

JP37JP@
+5VS
JUMP_43X118

TPS22966DPUR_SON14_2X3

U11,U59 change to SA00006FD00, S IC APE8990GN3B DFN 14P DUAL LOAD SW
VIH=1.2~5.5V
3.3V@82k/0.1uF=3.042ms
3.3V@47k/0.1uF=1.893ms

U59

R1055
82K_0402_5%
2
1

SUSP#

0701 update
2

1
2

+1.8VALW
1.8VS_ON

1
C1125
.1U_0402_16V7K
2
1
R1056
47K_0402_5%
1
C1128
.1U_0402_16V7K

2

4

+5VALW
1.35VS_ON

5
6
7

+1.35V_L

2

3

Rise Time:

1.8V@330pF = 485.28us
1.35V@330pF = 363.96us

JP38JP@

VIN1
VIN1

VOUT1
VOUT1

ON1

CT1

VBIAS

GND

ON2

CT2

VIN2
VIN2

VOUT2
VOUT2
GPAD

14
13
12

+1.8VS_OUT

+1.8VS

2

C1123
1 330P_0402_50V7K

2

1

JUMP_43X79

11
10

330P_0402_50V7K
C1127
+1.35VS_OUT

9
8
15

2

JP39JP@
+1.35VS
JUMP_43X79

TPS22966DPUR_SON14_2X3

+1.0VALW TO +1.0VS
+5VALW

0708:Change to SB00000PZ00 / need apply footprint

1
2
3

R1057
100K_0402_5%
C1130
4.7U_0603_6.3V6K
<30>

1

D
<10,22,30,31,32>

2
S

R1059
10K_0402_5%

S

S

Q69
2N7002K_SOT23-3

2

2 SUSP
G
Q71 @
2N7002K_SOT23-3

G

3

G
Q70
2N7002K_SOT23-3

+1.0VS_R

D
C1131

.1U_0402_16V7K
3

1

1

2

2

SUSP#
1

1
1

1.0VS_GATE

D
SUSP

3

1

@
R1052
470_0603_5%

+5VALW
2
1
R1061
10K_0402_5%

SUSP

SUSP

2

4

1

2

2

+1.0VS

1

8
7
6
5

2

C1129
4.7U_0603_6.3V6K

3

U60
ME4856_SO8

3

+1.0VALW

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2013/04/12

2014/04/12

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

DC INTERFACE

Z5WAL_Bay Trail M_LA‐B211P
Sheet

Monday, April 07, 2014

E

25

of

39

Rev
1.0