Gigabyte GA-b350m-d2 rev 1.02 schematic

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5

4

GA-B350M-D2
PAGE
D

TITLE

3

PAGE

Revision : 1.02

2

1

TITLE

26

ATX ,F_PANEL

27

PM PWR,VPP_MEM,VDDCR_SOC_S5

01

COVER SHEET

28

DDR POWER ,5VDUAL ,3VDUAL

02

BOM & PCB MODIFY HISTORY

29

RTL8111G

03

BLOCK DIAGRAM

30

FAN, COM

04

CPU DDR4 MEMORY

31

VGA

05

CPU DDI, CONTROL

32

CPU SMD CAP BOTTOM

06

CPU GFX, GPP, SB, GND

33

CPU SMD CAP TOP

07

CPU MISC

08

CPU POWER

09

CPU CLK, USB3, SPI ,LPC

10

DDR4 CHANNEL A

11

DDR4 CHANNEL B

12

PM CLK, SPI, MISC

13

PM USB

14

PM SATA, GPP

15

PM POWER, GND

16

PCIEx16 ,PCIEx1 Slot

17

DVI

18

IT8628, KB_MS_USB

19

F_USB ,F_USB30, R_USB30

20

A_VDD1V8, A_VDDPS5

21

ALC887 CODEC

22

AUDIO JACK

23

POWER SEQ, A_VDDP

24

PWM ISL95712

25

VCORE MOS

D

C

B

A

C

B

A

2015.12.30--B.L

Title

COVER SHEET
Size
Document Number
Custom
Date:
5

4

3

2

Rev

GA-B350M-D2

Tuesday, November 01, 2016

Sheet
1

1.02
1

of

33

5

4

3

Model Name:GA-B350M-D2

Date

Change Item
0.1T New BOM release

PCB:0.1T

For 機機機 BOM

2016.05.25

0.1 New BOM release

PCB:0.1

New Model ,Modify B350M-DS3H Rev0.1

2016.05.26

0.2 E-BOM release

PCB:0.2

2016.07.29

1.0A E-BOM release

PCB:1.0

2016.07.29

1.0A New BOM release

PCB:1.0

2016.08.17

1.0B E-BOM release

PCB:1.01

2016.08.26

1.0C P-BOM release

PCB:1.02

P-Code: U16130-0
D

Reason

2016.05.20

C

1

Version: 1.02

Component value change history

D

2

Modify VDDCR_SOC_S5 ,CPUVDD_EN schematic
Modify DDR A0/B0 to A1/B1
Remove choke co-lay ,improve power ripple
Modify PWM with PSU boot issue
Modify FUSB30 port1 with PROM1 DG assign port
Modify Erp circuit

New Model ,Modify A320M-DS2 Rev0.2
Modify DDR A0/B0 to A1/B1
Remove choke co-lay ,improve power ripple
Modify PWM with PSU boot issue
Modify Erp circuit
Change B350 ,Single BIOS

C

Add F_USB30 redriver
CPU PWM Current-DAC
Modify CPU socket MLCC DFM ,Update DB_PORT footprint
Modify CPU VRHOT 串分 ,down-size 2.2uf/4 ,Modify CPU_FAN White ,
Modify CPU PWM stardust 分 ,MOS vishay to on

Circuit or PCB layout change for next version
For 機機機

2016.05.19

Rev 0.1T Gerber-out

2016.05.24

Rev 0.1 Gerber-out

Modify from B350M-DS3H Rev0.1

2016.05.26

Rev 0.2 Gerber-out

Modify VDDCR_SOC_S5 ,CPUVDD_EN schematic

2016.07.28

Rev 1.0 Gerber-out

Modify DDR A0/B0 to A1/B1
Remove choke co-lay ,improve power ripple
Modify PWM with PSU boot issue
Modify FUSB30 port1 with PROM1 DG assign port
Modify Erp circuit

B

2016.07.28

Rev 1.0 Gerber-out

Modify from A320M-DS2 Rev0.2
Modify DDR A0/B0 to A1/B1
Remove choke co-lay ,improve power ripple
Modify PWM with PSU boot issue
Modify Erp circuit

2016.08.16

Rev 1.01 Gerber-out

Add F_USB30 redriver
CPU PWM Current-DAC

2016.08.25

Rev 1.02 Gerber-out

Modify CPU socket MLCC DFM ,Update DB_PORT footprint ,down-size 2.2uf/4

B

A

A

Title

BOM & PCB HISTORY
Size

Document Number
Custom
Date:
5

4

3

2

Rev

GA-B350M-D2
Sheet

Tuesday, November 01, 2016
1

1.02
2

of

33

5

4

3

2

1

UNGANGED MODE 64BIT
DDR4 2133/2400/2666

AMD AM4
D

1 X16 or X8 PCIE+ VIDEO I/F
DVI

DP1

17

UNBUFFERED
DDR4 DIMM2

11

UNBUFFERED
DDR4 DIMM1

10

UNGANGED MODE 64BIT
DDR4 2133/2400/2666

1 X4 PCIE GEN3 I/F with I/O HUB
PCIE GEN3 x4 or

DDR4 FIRST LOGICAL DIMM

PCIE GEN3 x2 +
VGA

DP2

31

D

SATA GEN3 x2 or SATA Express x1
USB3.1 GEN1 x4

PCIE 0~7/0~15

PCIE SLOT x8/x16
16

AZALIA
LPC I/F
INT RTC

USB31 Gen1

HW MONITOR

R_USB30

R_USB30

R_USB30

Port 0

Port 1

Port 2

ACPI
LPC

C

SPI BIOS

SPI I/F

9

19

ITE LPC SIO IT8628
18

TPM Header

ALC887-VD2
HD AUDIO CODEC
21,22

HD AUDIO I/F

4,5,6,7,8,9

DB_PORT

19

PS2 KB/MS
CPU/SYS FAN
HWM

29

COM
F_PANEL

C

18

18

4X PCIE

GEN3

USB30-1

USB30-0

19

19

USB31 GEN1 (0~5)

SATA GEN3

I/O HUB
Promontory

SATA_EXPRESS/SATA GEN3

1 X4 PCIE GEN3 I/F
with APU

B

VCORE /VCORE_SOC
ISL95712+ ISL6625 4+3PHASE
24,25
SATA#0

SATA#1

14

14

SATA#2

SATA#3

14

14

19

USB-2
19

USB-1
19

USB-0

USB20 (0~5)

19

GPP4

USB3.1 GEN2 x2

USB3.1 GEN1 x6

GIGABIT LAN
RTL8111G
29

48MHz

USB2.0 x6
USB-4
18

USB-5
18

GPP5/GPP6

R_USB31-0

USB31 GEN2 (0~1)

29

29
B

PCIE GEN2 x8
USB-3

28

VDDIO_MEM : RT8120
DDRVTT : NCT3103S
VPP_MEM : RT8068A

SATA GEN3 x4

9

PCIE SLOT x1
PCIEX1_1
16
PCIEX1_2

CLK From AM4
GFX_CLK : PCIEx16
GPP_CLK(0~3)
0: n/a
1: n/a
2: Promontory
3: n/a

9

SATA Express x 2
or SATA GEN3 x4
CLK Buffer (Promontory )
GPP_CLK0~7
0,1,2,3 : n/a
4 : LAN

5 : PCIEx1_1
6 : PCIEx1_2
7: n/a

12,13,14,15

12

A

A

Title

BLOCK DIAGRAM
Size
Document Number
Custom
Date:
5

4

3

2

Rev

GA-B350M-D2

Tuesday, November 01, 2016

Sheet
1

1.02
3

of

33

5

4

3

MDA[0..63]

AM4A

2

10

1

MDB[0..63]

AM4I

MEMORY A

10

MAAA0
MAAA1
MAAA2
MAAA3
MAAA4
MAAA5
MAAA6
MAAA7
MAAA8
MAAA9
MAAA10
MAAA11
MAAA12
MAAA13

MAAA[0..13]

D

AA32
T32
T35

T31
R30
R33
R32
P34
P30
P31
AA36
P33
N35
AE32

MA_DATA[0]

MA_ADD[1]

MA_DATA[1]

MA_ADD[2]

MA_DATA[2]

MA_ADD[3]

MA_DATA[3]

MA_ADD[4]

MA_DATA[4]

MA_ADD[5]

MA_DATA[5]

MA_ADD[6]

MA_DATA[6]

MA_ADD[7]

MA_DATA[7]

MA_ACTMA_BG0
MA_BG1

10
10

MA_BA0
MA_BA1

MA_ACTMA_BG0
MA_BG1

M35
N31
N32

MA_ADD[9]

MA_DATA[8]

MA_ADD[10]

MA_DATA[9]

MA_ADD[11]

MA_DATA[10]

MA_ADD[12]

MA_DATA[11]

MA_ADD[13]

MA_DATA[12]

MA_ACT_L

MA_DATA[14]

MA_BG[0]

MA_DM[0..8]

MA_DATA[15]
MA_DATA[16]

MA_BA0

MA_BA1

AA35
AA33

MA_BANK[0]

MA_DATA[17]

MA_BANK[1]

MA_DATA[18]

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DM8

K19
J23
G26
H30
AJ31
AM31
AL29

AL26
G34

MA_DM[0]

MA_DATA[21]

MA_DM[1]

MA_DATA[22]

MA_DM[2]

MA_DATA[23]

DQSA0
-DQSA0
DQSA1
-DQSA1
DQSA2
-DQSA2
DQSA3
-DQSA3
DQSA4
-DQSA4
DQSA5
-DQSA5
DQSA6
-DQSA6
DQSA7

-DQSA7
DQSA8
-DQSA8

H19
G19
F23
G23
F27
F26
F30
E30
AJ33
AJ34
AN32
AN33
AP29
AN29
AP26
AN26
H34
H33

MA_DQS_H[0]

MA_DATA[30]

MA_DQS_L[0]

MA_DATA[31]

MA_DATA[19]

MA_DM[4]

MA_DATA[24]

MA_DM[5]

MA_DATA[25]

MA_DM[6]

MA_DATA[26]

MA_DM[7]

MA_DATA[27]

MA_DM[8]

MA_DATA[28]

10
10
10
10

MA_CLKH2
MA_CLKL2

MA_CLKH3
MA_CLKL3

MA_CLKH2
MA_CLKL2
MA_CLKH3
MA_CLKL3

MA_DQS_L[1]

MA_DATA[32]

MA_DQS_H[2]

MA_DATA[33]

MA_DQS_L[2]

MA_DATA[34]

MA_DQS_H[3]

MA_DATA[35]

MA_DQS_L[3]

MA_DATA[36]

MA_DQS_H[4]

MA_DATA[37]

MA_DQS_L[4]

MA_DATA[38]

MA_DQS_H[5]

MA_RSTMA_EVENT-

10
10

MA_DATA[39]

MA_DQS_H[6]

MA_DATA[40]

MA_DQS_L[6]

MA_DATA[41]

MA_DQS_H[7]

MA_DATA[42]

MA_DQS_L[7]

MA_DATA[43]

MA_DQS_H[8]

MA_DATA[44]

MA_DQS_L[8]

MA_DATA[45]

MA_CLK_H[0]

MA_DATA[47]

10
10

B

10
10

MODT_A2
MODT_A3

MA_CLK_H[1]

MA_DATA[48]

MA_CLK_L[1]

MA_DATA[49]

MA_CLK_H[2]

MA_DATA[50]

MA_CLK_L[2]

MA_DATA[51]

MA_CLK_H[3]

MA_DATA[52]

MA_CLK_L[3]

MA_DATA[53]

10
10
10
10
10
10

MA_RSTMA_ENENT-

L33
W 35

MA0_CKE[0]

MA_DATA[57]

MA0_CKE[1]

MA_DATA[58]

MA1_CKE0
MA1_CKE1

M32
M30
M33
L34

MA1_CKE[0]

MA_DATA[59]

MA1_CKE[1]

MA_DATA[60]

MA0_ODT[0]

MA_DATA[62]

MA0_ODT[1]

MA_DATA[63]

MODT_A2
MODT_A3

AD35
AF31
AD33
AF34

MA_RESET_L

MA_DATA[55]

MAAA17
MAAA16
MAAA15
MAAA14

MA_DATA[61]

MA1_ODT[1]

MA_CHECK[0]

MA_ALERTMA_PAROUT

MA0_CS_L[0]

MA_CHECK[2]

MA0_CS_L[1]

MA_CHECK[3]

MA1_CS0MA1_CS1-

MA1_CS_L[0]

MA_CHECK[4]

MA1_CS_L[1]

MA_CHECK[5]

MAAA17
MAAA16
MAAA15
MAAA14

AF33
AB34
AD32
AB35

MA_ADD_17

MA_CHECK[6]

N34

Y33

MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23

11
11
11

MB_ACTMB_BG0
MB_BG1

11
11

F29
J30
H31
F32
J29
G29
E31
G31
AH34

AJ30
AK30
AL34
AH31
AH32
AK33
AK32
AM34
AM33
AP31
AR33
AL32
AL31
AP34
AP32
AR31
AK29
AM28
AL28
AM30
AN30
AP28
AR28
AK27
AK26
AP25
AR25
AN27
AM27
AL25

AM25

MA_CHECK[7]

F33
G32
K31
K32
E33
E34
J32
J33

MA_RAS_L_ADD[16]

MB_BA0
MB_BA1

MB_DM[0..8]

MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31

MB_ACTMB_BG0

MB_BG1

M38
M36
M39

MB_BA0
MB_BA1

AD38
AC37

MA_ZVDDIO_MEM_S3

MA_PAROUT

MA_ZVSS

Y34
AJ37

MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40

MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47

AM4 REV 0.92

MB_DATA[1]

MB_ADD[2]

MB_DATA[2]

MB_ADD[3]

MB_DATA[3]

MB_ADD[4]

MB_DATA[4]

MB_ADD[5]

MB_DATA[5]

MB_ADD[6]

MB_DATA[6]

MB_ADD[7]

MB_DATA[7]

MB_ADD[9]

MB_DATA[8]

MB_ADD[10]

MB_DATA[9]

MB_ADD[11]

MB_DATA[10]

MB_ADD[12]

MB_DATA[11]

MB_ADD[13]

MB_DATA[12]

MB_ACT_L

MB_DATA[14]

MB_BG[0]

11
11
11
11

MB_CLKH2
MB_CLKL2
MB_CLKH3
MB_CLKL3

MB_CLKH2
MB_CLKL2
MB_CLKH3
MB_CLKL3

MB_DATA[15]

MB_BANK[0]

MB_DATA[17]

MB_BANK[1]

MB_DATA[18]

MB_DM[0]

MB_DATA[21]

MB_DM[1]

MB_DATA[22]

MB_DM[2]

MB_DATA[23]

MB_DM[4]

MB_DATA[24]

MB_DM[5]

MB_DATA[25]

MB_DM[6]

MB_DATA[26]

MB_DM[7]

MB_DATA[27]

MB_DM[8]

MB_DATA[28]

MB_DQS_H[0]

MB_DATA[30]

MB_DQS_L[0]

MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

11
11

11
11

MA_CHK0
MA_CHK1
MA_CHK2
MA_CHK3
MA_CHK4
MA_CHK5
MA_CHK6
MA_CHK7

11

11

MA_CHK[0..7]

11
11
11
11

10

AR23
AR48

39.2/4/1
40.2/4/1/X

VDDIO_MEM

11
11

MB_RSTMB_EVENT-

MB_DATA[31]

U39
V39
V38
W 38

W 37
Y37
Y39
AA39

MB_CLK_H[0]

MB_DQS_L[1]

MB_DATA[32]

MB_DQS_H[2]

MB_DATA[33]

MB_DQS_L[2]

MB_DATA[34]

MB_DQS_H[3]

MB_DATA[35]

MB_DQS_L[3]

MB_DATA[36]

MB_DQS_H[4]

MB_DATA[37]

MB_DQS_L[4]

MB_DATA[38]

MB_DQS_H[5]

MB1_CKE0
MB1_CKE1

MB_DATA[39]

MB_DQS_H[6]

MB_DATA[40]

MB_DQS_L[6]

MB_DATA[41]

MB_DQS_H[7]

MB_DATA[42]

MB_DQS_L[7]

MB_DATA[43]

MB_DQS_H[8]

MB_DATA[44]

MB_DQS_L[8]

MODT_B2
MODT_B3

MB1_CS0MB1_CS1MAAB17
MAAB16
MAAB15
MAAB14

MB_DATA[45]
MB_DATA[47]

MB_CLK_H[1]

MB_DATA[48]

MB_CLK_L[1]

MB_DATA[49]

MB_CLK_H[2]

MB_DATA[50]

MB_CLK_L[2]

MB_DATA[51]

MB_CLK_H[3]

MB_DATA[52]

MB_CLK_L[3]

MB_DATA[53]

MB_ALERTMB_PAROUT

MB_RESET_L

MB_DATA[55]

MB0_CKE[0]

MB_DATA[57]

MB0_CKE[1]

MB_DATA[58]

MB1_CKE[0]

MB_DATA[59]

MB1_CKE[1]

MB_DATA[60]

AF39
AH36
AF37
AH38

MB0_ODT[0]

MB_DATA[62]

MB0_ODT[1]

MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31

AK39
AL37
AN36
AN39
AK38
AK36
AM39
AN38

MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39

AR36
AR37
AU37
AV37
AP37
AP38
AT36
AU38

MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47

AW 35
AU35
AW 32

AU32
AV36
AW 36
AW 33
AV33

MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55

AW 30
AV30
AW 27
AW 26
AV31
AU31
AV28
AV27

MDB56
MDB57
MDB58
MDB59
MDB60
MDB61

MDB62
MDB63

F38
F36
H39
J39
E37
E39
H36
H37

MB_CHK0
MB_CHK1
MB_CHK2
MB_CHK3
MB_CHK4
MB_CHK5
MB_CHK6
MB_CHK7

C

MEM CHB

MB_DATA[63]

MB1_ODT[0]
MB1_ODT[1]

MB_CHECK[0]
MB_CHECK[1]

MB0_CS_L[0]

MB_CHECK[2]

MB0_CS_L[1]

MB_CHECK[3]

MB1_CS0MB1_CS1-

AE37
AG39
AE38
AG36

MB1_CS_L[0]

MB_CHECK[4]

MB1_CS_L[1]

MB_CHECK[5]

MAAB17
MAAB16
MAAB15
MAAB14

AH37
AD36
AF36
AD39

MB_ADD_17

MB_CHECK[6]
MB_CHECK[7]

MB_RAS_L_ADD[16]

B

B0

MB_CHK[0..7]

MB_CAS_L_ADD[15]

MB_CHK[0..7]

B1

11

MB_WE_L_ADD[14]
MB_ALERT_L

MB_ZVDDIO_MEM_S3

MB_PAROUT

MB_ZVSS

Y36
AJ39

MB_ZVDDIO
MB_ZVSS

AR27
AR49

39.2/4/1
40.2/4/1/X

VDDIO_MEM

Place within 1" of APU.

AM4 REV 0.92

Place within 1" of APU.

PART 1 OF 12

B36
E36

C39
D38
A35
C36
B38
C38

MB_EVENT_L

L37
K37
L39
L36

MB_ALERTN37
MB_PAROUT AB38

MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23

MB_CLK_L[0]

MB_DATA[61]

MODT_B2
MODT_B3

A31
B31
B34
C35
B30
C30
B33
A34

D

MB_DQS_L[5]

MB_DATA[56]

MB1_CKE0
MB1_CKE1

MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15

MB_DQS_H[1]

MB_DATA[54]

11
11

A26
C26
A29
C29
A25
B25
A28
B28

MB_DM[3]

B22
A22
C27
B27
C33
C32
B37
A37
AM37
AM36
AT38
AT39

AU34
AV34
AU28
AU29
G38
G37

MB_RSTK35
MB_EVENT- AA38

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7

MB_BG[1]

MB_DATA[19]

MB_DM0 C21
MB_DM1 D26
MB_DM2 A32
MB_DM3 D37
MB_DM4 AL38
MB_DM5 AR39
MB_DM6 AT35

MB_DM7AW 29
MB_DM8 F39

D20
B21
B24
C24
A20
C20
A23
C23

MB_ADD[8]

MB_DATA[46]

MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55

MA_ZVDDIO
MA_ZVSS

MB_ADD[1]

MB_DATA[29]

MA_WE_L_ADD[14]
MA_ALERT_L

MB_DATA[0]

MB_DATA[16]

DQSB0
-DQSB0
DQSB1
-DQSB1
DQSB2
-DQSB2
DQSB3
-DQSB3
DQSB4
-DQSB4
DQSB5
-DQSB5
DQSB6
-DQSB6
DQSB7
-DQSB7
DQSB8
-DQSB8

MA_CHK[0..7]

MA_CAS_L_ADD[15]

MB_ADD[0]

MB_DATA[20]

11

MA1_ODT[0]

AC33
AE35
AC34
AE34

MA_ALERTMA_PAROUT

J26
J27
G28
H28
H25
G25
E28
H27

AC36
U36
U37
T38

T37
R39
R36
P39
R38
P36
AC39
P37
N38
AG38

MB_DATA[13]

MA_EVENT_L

MA_CHECK[1]

MA1_CS0MA1_CS1-

MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15

MA_CLK_L[0]

MA_DATA[56]

MA1_CKE0
MA1_CKE1

H22
G22
E24
J24
F21
J21
H24
F24

MA_DQS_L[5]

MA_DATA[54]

10
10

MAAB[0..13]

MA_DQS_H[1]

MA_DATA[46]

T34
U34
U33

V33
V35
V36
V32
W 32

11

MAAB0
MAAB1
MAAB2
MAAB3
MAAB4
MAAB5
MAAB6
MAAB7
MAAB8
MAAB9
MAAB10
MAAB11
MAAB12
MAAB13

MA_DM[3]

MA_DATA[29]

C

MDA0

MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7

MA_BG[1]

MA_DATA[20]

10

E18
J18
J20
H21
H18
F18
G20
F20

MA_ADD[8]

MA_DATA[13]

10
10
10

11

MEMORY B

MA_ADD[0]

PART 9 OF 12

AM4/[10SC1-P01331-01R_10SC1-P01331-02R]

AM4/[10SC1-P01331-01R_10SC1-P01331-02R]

MEM CHA
AM4

10

MDA[0..63]

10

MAAA[0..16]

10

DQSA[0..8]

A

10

-DQSA[0..8]

MDA[0..63]
MAAA[0..16]
DQSA[0..8]

11

MDB[0..63]

11

MAAB[0..16]

11

-DQSA[0..8]

11

DQSB[0..8]
-DQSB[0..8]

MDB[0..63]
MAAB[0..16]
A

DQSB[0..8]

-DQSB[0..8]

Title

APU DDR4
A0

Size
Document Number
Custom

A1

AM3RM/SC/BL/MB/[12KRC-04K813-01R]
Date:
5

4

3

2

Rev

GA-B350M-D2
Sheet

Tuesday, November 01, 2016
1

1.02
4

of

33

5

APU_SIC

1K/4/1

APU_SID

AR34

300/4

APU_PWRGD

AR33

300/4

APURSTL

AM4C

DISPLAY/SVI2/JTAG/TEST

31
31

VGA

DP2_TXP0
DP2_TXN0

DP2_TXP0
DP2_TXN0

B6
B7

Placed within 1500 mils from APU

DP2_TXP[0]

DP_ZVSS

DP2_TXN[0]

DP_AUX_ZVSS
DP_BLON

31
31

AC25
100p/4/NPO/50V/J

DP2_TXP1
DP2_TXN1

DP2_TXP1
DP2_TXN1

A7
A8

DP2_TXP[1]

DP_DIGON

DP2_TXN[1]

DP_VARY_BL

C8
C9

DP2_TXP[2]

B9
B10

DP2_TXP[3]

DP1_TXP0
DP1_TXN0

D4
D5

DP1_TXP[0]
DP1_TXN[0]

DP1_HPD

DP1_TXP1
DP1_TXN1

D7
D8

DP1_TXP[1]

DP0_AUXP

DP1_TXN[1]

DP0_AUXN

DP1_TXP2
DP1_TXN2

F8
G8

DP1_TXP[2]

DP2_TXN[2]

DP2_AUXP
DP2_AUXN

AR50

1K/4/1

APU_SVT

AR41
AR43

1K/4/1/X
1K/4/1/X

APU_SVC

17
17

DP1_TXP0
DP1_TXN0

17
17

DP1_TXP1
DP1_TXN1

17
17

DP1_TXP2
DP1_TXN2

DP2_HPD

DP1_AUXN

DP0_HPD

AR44
AR45

A_VDD1V8

1K/4/1/X
1K/4/1/X

APU_SVD

17
17

0

SVD
0

DP1_TXP3
DP1_TXN3

DP1_TXP3
DP1_TXN3

Boot voltage

1

1.0

1

0

0.9

1

1

0.8

E9
F9

DP1_TXP[3]

D2
C2

DP0_TXP[0]

C3
B3

DP0_TXP[1]

TEST5

DP0_TXN[1]

TEST6

B4
A4

DP0_TXP[2]

TEST10

DP0_TXN[2]

TEST14

C5
C6

DP0_TXP[3]

TEST16

DP0_TXN[3]

TEST17
TEST19

24

APU_SVC
APU_SVD
APU_SVT

APU_SVC
APU_SVD
APU_SVT

D17
C17
A17

SVC

TEST18

APU_PWRGD
E16
AR52
0/4 APURSTL B16

PWROK

TEST31

RESET_L

TEST40
DP_STEREOSYNC

18

A_VDD1V8

AR68

HDTP_PWR
0/4/SHT/20/X

AR72
AR107
AR70
AR71

1K/4/1
1K/4/1/X

1K/4/1
1K/4/1

APU_TDI
APU_TDO
APU_TCK
APU_TMS

AR108
AR73

1K/4/1/X
1K/4/1

APU_DBRDY
APU_DBREQ-

AR67

1K/4/1

APU_TRST-

DP1_AUXP
DP1_AUXN
DP1_HPD

17
17
17

APU_SIC
APU_SID

AR35
8.2K/4/X

G10
H10
H9

AQ1
DP0_HPD

AR46

D

THERMTRIPO

THERMTRIPO 18

AC13
0.1u/4/Y5V/16V/Z/X

100K/4/1
AR37

1K/4/1/X AQ1_2

THERMTRIP-

L23
M22
D13
P28
AB4
C12
B12
C11
D11
A13
H16
G16

APU_TEST4
APU_TEST5
APU_TEST6
APU_TEST10
APU_TEST14
APU_TEST15
APU_TEST16
APU_TEST17
APU_TEST11
APU_TEST19
APU_TEST18

TP5

E6

E7
AA30
W 30
K14

APU_TEST28_H
APU_TEST28_L
APU_TEST31
APU_TEST40
APU_STESYNC

TP8
TP9
TP13
TP14

AL8
AM24
AN9

AM4R1
CORETYPE0
CORETYPE1

A16

APU_TEST41

TP1
TP2

TP3

TP6

THERMTRIP-

AR1

1K/4/1/X

AR2
AR3
AR5
AR62
AR20

1K/4/1/X
1K/4/1/X
1K/4/1/X
1K/4/1
1K/4/1

AR36

0/4

THERMTRIPO

SVT
TEST28_L

18

DP1_AUXP
DP1_AUXN
DP1_HPD

SVD
TEST28_H

24 APU_PWRGD
26
APURST-

F11
G11
D10

DP0_TXN[0]

TEST11

24

31
31
31

DP1_TXN[3]

TEST15

24

DP2_AUXP
DP2_AUXN
DP2_HPD

MMBT2222A/SOT23/600mA/40/X

TEST47

C

DP2_AUXP
DP2_AUXN
DP2_HPD

2K/4/1
150/4/1

A_VDD1V8

1.1

0

A10
A11
E10

AR29
AR26

DP1_TXN[2]

TEST4

SVC

DP_ZVSS
DP_A_ZVSS

DP2_TXN[3]
DP1_AUXP

DVI

F12
E12
G13
H13
H12

VCC3

D

A_VDD1V8

1

3

1K/4/1

AR40

2

1

AR39

3

2

A_VDD1V8

4

APU_SIC
APU_SID
APU_ALERTAPU_PROCHOTTHERMTRIP-

B18
C18
D16
H15

A19

SIC

AM4R1

SID

CORETYPE[0]

ALERT_L

CORETYPE[1]

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRSTAPU_DBRDY
APU_DBREQ-

A14
C14
C15
B15
B13
E13
D14

TDI

PROCHOT_L
THERMTRIP_L

TEST41

VDDCR_CPU_SENSE

TDO

VDDCR_SOC_SENSE

TCK

VDDIO_MEM_S3_SENSE

TMS

VSS_SENSE_A

F14
E15
G14
F15

C

AM4R1

23,27

CORETYPE1

7,20,23

TP15

COREFB+
VNB_FB+

24
24

COREFB-

24

TRST_L
DBRDY

VDDP_SENSE

DBREQ_L

VSS_SENSE_B

AL22
AM23

CORETYPE0

CORETYPE1

AR30
AR13

1K/4/1
1K/4/1

APU_STESYNC

AR22
AR21

1K/4/1
1K/4/1/X

AM4 REV 0.92
PART 3 OF 12

A_VDD18S5
3VDUAL
A_VDD1V8

AM4/[10SC1-P01331-01R_10SC1-P01331-02R]

APU_STESYNC: high=>HDMI, low=>NO HDMI

AM4R1

A_Q4

B

VCC3

A_VDD1V8

1

IN(H)

SEL

6

2

GND

VCC

5

3

IN(L)

OUT

4

AR117

CORETYPE1

8.2K/4

3VDUAL

B

3VDUAL
A_Q4_4
ABC24
1u/4/X5R/6.3V/K

AR51

1K/4/1

APU_ALERT-

AR61

1K/4/1

THERMTRIP-

AR32

1K/4/1

APU_PROCHOT-

APU_PROCHOT- 24

NC7SB3157P6X_NL/SC70-6/[10TT1-123157-10R]

AM4 CPU CoreType
CORETYPE 1 CORETYPE 0 Family / Model Numbers

A

AM4 APU TYPE

0 BR

0

Family 15 h / Models 60 h- 6 Fh

TYPE 0

0

1

Reserved

TYPE 1

1 ST

0

Family 17 h / Models 00 h- 0 Fh

TYPE 2

1 RV

1

Family 17 h / Models 10 h- 1 Fh

TYPE 3

A

Title

CPU DDI, CONTROL
Size
Document Number
Custom
Date:
5

4

3

2

Rev

GA-B350M-D2
Sheet

Tuesday, November 01, 2016
1

1.02
5

of

33

8

7

6

5

4

AM4G

AM4B
PCIE

14
14

AE8
AD8

A_RX0P
A_RX0N

14
14
14
14
14
14

P_HUB_TXP[0]

P_HUB_RXN[0]

P_HUB_TXN[0]

AB8
AA8

P_HUB_RXP[1]

P_HUB_TXP[1]

P_HUB_RXN[1]

P_HUB_TXN[1]

A_RX2P
A_RX2N

Y6
Y7

P_HUB_RXP[2]

P_HUB_TXP[2]

P_HUB_RXN[2]

P_HUB_TXN[2]

W4
W5

P_HUB_RXP[3]

P_HUB_TXP[3]

P_HUB_RXN[3]

P_HUB_TXN[3]

AE4
AE5

A_TX0P_C
A_TX0N_C

AC1
AC2

0.22u/4/X5R/6.3V/K
0.22u/4/X5R/6.3V/K

AA5
AB5

A_TX1P_C
A_TX1N_C

AC3
AC4

0.22u/4/X5R/6.3V/K
0.22u/4/X5R/6.3V/K

AC6
AC7

A_TX2P_C
A_TX2N_C

AC5
AC6

0.22u/4/X5R/6.3V/K
0.22u/4/X5R/6.3V/K

AD5
AD6

A_TX3P_C
A_TX3N_C

AC7
AC8

0.22u/4/X5R/6.3V/K
0.22u/4/X5R/6.3V/K

D

AR9
AT9

P_GPP_RXP[0]

P_GPP_TXP[0]

P_GPP_RXN[0]

P_GPP_TXN[0]

AM9
AM10

P_GPP_RXP[1]

P_GPP_TXP[1]

P_GPP_RXN[1]

P_GPP_TXN[1]

AR10
AP10
AP11
AN11
EXP_A_RXP0
EXP_A_RXN0
EXP_A_RXP1
EXP_A_RXN1
EXP_A_RXP2
EXP_A_RXN2
EXP_A_RXP3
EXP_A_RXN3
EXP_A_RXP4
EXP_A_RXN4

C

F6
F5
G5
G4
H7
H6
J6
J5
K8
K7

P_GPP_RXP[2]/SATA_RX0P

P_GPP_TXP[2]/SATA_TX0P

P_GPP_RXN[2]/SATA_RX0N

P_GPP_TXN[2]/SATA_TX0N

P_GPP_RXP[3]/SATA_RX1P

P_GPP_TXP[3]/SATA_TX1P

P_GPP_RXN[3]/SATA_RX1N

P_GPP_TXN[3]/SATA_TX1N

P_GFX_RXP[0]

P_GFX_TXP[0]

P_GFX_RXN[0]

P_GFX_TXN[0]

P_GFX_RXP[1]

P_GFX_TXP[1]

P_GFX_RXN[1]

P_GFX_TXN[1]

P_GFX_RXP[2]

P_GFX_TXP[2]

P_GFX_RXN[2]

P_GFX_TXN[2]

P_GFX_RXP[3]

P_GFX_TXP[3]

P_GFX_RXN[3]

P_GFX_TXN[3]

P_GFX_RXP[4]

P_GFX_TXP[4]

P_GFX_RXN[4]

P_GFX_TXN[4]

EXP_A_RXP5
EXP_A_RXN5

K5
K4

P_GFX_RXP[5]

P_GFX_TXP[5]

P_GFX_RXN[5]

P_GFX_TXN[5]

EXP_A_RXP6
EXP_A_RXN6

L7
L6

P_GFX_RXP[6]

P_GFX_TXP[6]

P_GFX_RXN[6]

P_GFX_TXN[6]

EXP_A_RXP7
EXP_A_RXN7

M6
M5

P_GFX_RXP[7]

P_GFX_TXP[7]

P_GFX_RXN[7]

P_GFX_TXN[7]

EXP_A_RXP8
EXP_A_RXN8

N8
N7

P_GFX_RXP[8]

P_GFX_TXP[8]

P_GFX_RXN[8]

P_GFX_TXN[8]

EXP_A_RXP9
EXP_A_RXN9

N5
N4

EXP_A_RXP10 P7
EXP_A_RXN10 P6
EXP_A_RXP11 R6
EXP_A_RXN11 R5
EXP_A_RXP12 T8
EXP_A_RXN12 T7

P_GFX_RXP[9]

P_GFX_TXP[9]

P_GFX_RXN[9]

P_GFX_TXN[9]

P_GFX_RXP[10]

P_GFX_TXP[10]

P_GFX_RXN[10]

P_GFX_TXN[10]

P_GFX_RXP[11]

P_GFX_TXP[11]

P_GFX_RXN[11]

P_GFX_TXN[11]

P_GFX_RXP[12]

P_GFX_TXP[12]

P_GFX_RXN[12]

P_GFX_TXN[12]

A_TX0P
A_TX0N
A_TX1P
A_TX1N

14
14
14
14

A_TX2P
A_TX2N

14
14

A_TX3P
A_TX3N

14
14

AT12
AR12
AP13
AR13
AL13
AM13
AN14
AP14
D1
E1
E3
F3

EXP_A_TXP0
EXP_A_TXN0
EXP_A_TXP1
EXP_A_TXN1

F2
G2

EXP_A_TXP2
EXP_A_TXN2

G1
H1

EXP_A_TXP3
EXP_A_TXN3

H3
J3

EXP_A_TXP4
EXP_A_TXN4

J2
K2

EXP_A_TXP5
EXP_A_TXN5

K1
L1

EXP_A_TXP6
EXP_A_TXN6

L3
M3

EXP_A_TXP7
EXP_A_TXN7

M2
N2

EXP_A_TXP8
EXP_A_TXN8

N1
P1
P3
R3
R2
T2
T1
U1

PLACE THESE CAP CLOSE TO APU.

EXP_A_TXP9
EXP_A_TXN9
EXP_A_TXP10
EXP_A_TXN10
EXP_A_TXP11
EXP_A_TXN11
EXP_A_TXP12

EXP_A_TXN12

J15
L29
AJ11
A3
A6
A9
A12
A15
A18
A21
A24
A27
A30
A33
A36
B19
B23
B26
B29
B32
B35
C1
C22
C25
C28
C31
C34
C37

D6
D9
D12
D15
D18
D19
D21
D22
D23
D24
D25
D27
D29
D30
D31
D32
D33
D34
D35
D36
D39
E4
E5
E8
E11
E14
E17
E20
E21
E23

E26
E27
E29
E32

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

E35
E38
F1
F4
F17
F19
F22
F25
F28
F31
F34
F35
F37
G7
G21
G24
G27
G30
G33

G35
G36
G39
H4
H5
H8
H11
H14
H17
H20
H23
H26
H29
H32
H35
H38
J1
J4
J8
J9
J11
J13
J17
J19
J22
J25
J28
J31
J34
J35

J37
K10
K12
K18
K20
K21
K22
K23
K26
K27
K28
K29
K30

AF28
AF30
AG1
AG4
AG8
AG9
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AG25
AG27
AG28

AG29
AG30
AG31
AG32
AH10
AH12
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH29
AH30
AH33
AJ5
AJ8
AJ9
AJ13
AJ23
AJ25
AJ26
AJ27
AJ28
AJ29
AJ32
AJ35
AJ36

AJ38
AK1
AK4
AK10
AK12
AK14
AK22
AK25
AK28
AK31
AK35
AK37
AL9
AL11
AL24
AL27

AM4 REV 0.92
PART 7 OF 12

EXP_A_RXP14 U7
EXP_A_RXN14 U6
EXP_A_RXP15 V6
EXP_A_RXN15 V5

B

A_VDDP

AR25

196/4/1

P_VZDD

W8

P_GFX_RXP[13]

P_GFX_TXP[13]

P_GFX_RXN[13]

P_GFX_TXN[13]

P_GFX_RXP[14]

P_GFX_TXP[14]

P_GFX_RXN[14]

P_GFX_TXN[14]

P_GFX_RXP[15]

P_GFX_TXP[15]

P_GFX_RXN[15]

P_GFX_TXN[15]

P_ZVDDP

P_ZVSS
P0A_ZVSS
P0B_ZVSS

A_VDDP

AR28

1K/4/1

SATA_VZDD

AV7

AM4 REV 0.92

SATA_ZVDDP

SATA_ZVSS

U3
V3

EXP_A_TXP13
EXP_A_TXN13

V2

W2

EXP_A_TXP14
EXP_A_TXN14

W1
Y1

EXP_A_TXP15
EXP_A_TXN15

W7
V8
AT8
AV6

P_ZVSS
P0A_ZVSS
P0B_ZVSS
SATA_ZVSS

AR24
AR6
AR7
AR4

1

AM4H
GND

VSS

AM4/[10SC1-P01331-01R_10SC1-P01331-02R]
EXP_A_RXP13 T4
EXP_A_RXN13 T5

2

AM4J
GND

P_HUB_RXP[0]

A_RX1P
A_RX1N

A_RX3P
A_RX3N

3

AM4K
GND

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AL30
AL33
AL35
AL36
AL39
AM5
AM11
AM14
AM26
AM29
AM32
AM35
AM38
AN1
AN4
AN22
AN25
AN28
AN31
AN34
AN35
AN37
AP6
AP24
AP27
AP30
AP33

AP35
AP36
AP39
AR5
AR8
AR11
AR14
AR17
AR23
AR26
AR27
AR29
AR30
AR32
AR34
AR35
AR38
AT1
AT7
AT10
AT13
AT16
AT22
AT26
AT27
AT28
AT29
AT31
AT32
AT33

AT34
AT37
AU18
AU21
AU24

K33
L4
L5
L8
L9
L11
L13
L15
L17
L19
L21
L25
L27
L28
L30
L31
M1
M4
M8
M10
M12
M14
M16
M18

M20
M24
M26
M27
M28
N9
N11
N13
N15
N17
N19
N21
N23
N25
N27
N29
P4
P5
P8
P10
P12
R1
R4
R8
R9
R11
R13
R27
R29
T10

T12
T28
T30
U4
U5
U8
U9
U11

AM4 REV 0.92
PART 10 OF 12

AM4/[10SC1-P01331-01R_10SC1-P01331-02R]

GND & RSVD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

U13
U27
U29
U31
V1
V4

V7
V10
V12
V28
V30
W9
W 11
W 13
W 27
W 29
W 31
Y5
Y8
Y10
Y12
Y28
Y30
AA1
AA4
AA6
AA9
AA11
AA13
AA27
AA31
AA29
AB7
AB10
AB12
AB28

AB30
AC5
AC8
AC9
AC11
AC13
AC27
AC29
AC31
AD1
AD4
AD10
AD12
AD28
AD30
AE7
AE9
AE11
AE13
AE27
AE29
AE31
AF5
AF8
AF10
AF12

AU26
AU27
AU30

AU33
AU36
AU39
AV2
AV17
AV20
AV23
AV26
AV29
AV32
AV35
AV38
AW 4
AW 7
AW 10
AW 13
AW 16
AW 19
AW 22
AW 25
AW 28
AW 31
AW 34
AW 37

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD

VSS

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

RSVD
RSVD

AM4 REV 0.92
PART 8 OF 12

AM12
AT25
AR15
AP15
AN12
AN15
AT30
AW 24
AR24
A5
AD3
AB2
AH2
AL16
AL17
AL18
AL19
AL20
AL21
AM16
AM17
AM21
AN16
AN17

AN21
AP16
AP17
AP21
AR16
AR18
AR19
AR20
AR21
AT19
D28
E19
E22
E25
G17
J36
J38
K34
K38
R35
AB37
AH35
AK34

D

C

AM4 REV 0.92
PART 11 OF 12

AM4/[10SC1-P01331-01R_10SC1-P01331-02R]

AM4/[10SC1-P01331-01R_10SC1-P01331-02R]

B

Within 1500mil from APU

196/4/1
200/4/1/X
200/4/1/X
1K/4/1

PART 2 OF 12

Within 1500mil from APU

AM4/[10SC1-P01331-01R_10SC1-P01331-02R]
EXP_A_RXP[0..15]
EXP_A_RXN[0..15]
EXP_A_TXP[0..15]
EXP_A_TXN[0..15]

EXP_A_RXP[0..15] 16
EXP_A_RXN[0..15] 16
EXP_A_TXP[0..15] 16
EXP_A_TXN[0..15] 16

A

A

Title

CPU GFX, GPP, SB, GND
Size
Document Number
Custom
Date:
8

7

6

5

4

3

Rev

GA-B350M-D2

Tuesday, November 01, 2016
2

Sheet

1.02
6
1

of

33

8

7

6

5

4

3

2

1

VCC3
AR95
AR96

8.2K/4/X
2K/4/1/X

SYS_RSTL

3VDUAL

AR103

8.2K/4

PCIE_RST-

3VDUAL

AR104

8.2K/4

PCIE_WAKE-

3VDUAL

SMBCLK
SMBDATA

AM4D
ACPI/SD/AZ/GPIO/RTC/I2C/MISC

18

12,16

AR114
AR60

LPC_RSTPCIE_RST-

ARSTA_PERST-

33/4
33/4

RSMRST-

AU22
AL7
AP5

D

3VDUAL

SYS_RST-

1K/4/1/X S0A3_GPIO

AR112

18,23
18,27

LPCPME-

3VDUAL

AR111

8.2K/4

3VDUAL

AR110

1K/4/1/X SLP_S3-

3VDUAL

AR109

1K/4/1/X SLP_S5-

0/4/SHT/X PWRBTN-

AR0
18
-PSOUT
23
APU_PWOK
22/4
22P/4/N/50V/X

12,16,29,30 PCIE_WAKE-

PR68
PC17

PR69
PR70

SLP_S3SLP_S5-

SMBCLK
SMBDATA

PCIE_RST_L/EGPIO26

RSMRST_L

EGPIO95

23
27

S0A3_GPIO
S5_MUX

SLP_S3L
SLP_S5L

AT2
AP2

SLP_S3_L

EGPIO99

SLP_S5_L

EGPIO100

PWR_GOOD
WAKE_L/AGPIO2

EGPIO97

S0A3_GPIO
S5_MUX

3VDUAL
3VDUAL
3VDUAL

AR74
AR75

2.2K/4/1/X
15K/4/1

AR76
AR77

2.2K/4/1/X
15K/4/1

AR78
AR79

2.2K/4/1/X
15K/4/1

SLP_S5-

AR3
AP4

S0A3_GPIO/AGPIO10/SGPIO0_CLK

A_TEST0
A_TEST1
A_TEST2

AM6
AM7
AT3

TEST0

A_TEST0
ABC41
10P/4/NPO/50V/J

ABC42
10P/4/NPO/50V/J

A_TEST1

18

KBRST-

KBRST-

12,18 LPCPME12
AGPIO86

A_TEST2

AN24

LPCPMEAGPIO86

AL2
AW 17

S5_MUX_CTRL/EGPIO42

SCL0/I2C2_SCL/EGPIO113

AGPIO23

AN3

SCL1/I2C3_SCL/AGPIO19

TEST2

SDA1/I2C3_SDA/AGPIO20

AGPIO3

AGPIO86

AGPIO4
AGPIO6

AGPIO23/SGPIO0_LOAD

AGPIO8
GENINT1_L/AGPIO89
GENINT2_L/AGPIO90

ABC37
10P/4/NPO/50V/J/X
19

A_USB_OC1

A_USB_OC1

RTC_INTC

A_AZBCLK AW 3
AV3
AZ_SDIN1 AU5
8.2K/4
AZ_SDIN2 AV4
8.2K/4
A_AZRSTL AU1
22/4
A_AZSYNC AU2
22/4
A_AZSOUT AU4
22/4

AR18

21 AZ_BIT_CLK
21 AZ_SDATA_IN0

22/4

AR115
AR116
AR55
AR54
AR19

21
-AZ_RST
21
AZ_SYNC

21 AZ_SDATA_OUT

AT23
AV24
AT24
AL23
AR22
AL1
AM1
AR1
AP1

CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92

SATA_ACT_L/AGPIO130

CLK_REQ1_L/AGPIO115

AGPIO40/SGPIO0_DATAIN

A_AZRSTL

AR123

1K/4/1

A_AZBCLK

AR124

1K/4/1

A_AZSYNC

AR125

1K/4/1

A_AZSOUT

AR126

AR94

AT6
AR6
AP22
AN8
AP7
AN2
AV22
AU23
AM22
AR4

A_GPIO3

SMBCLK 10,11,24,27,31
SMBDATA 10,11,24,27,31
SMBCLK1 16

SMBDATA1 16

A_GPIO3

AGPIO89
AGPIO40

AR91
AR92

8.2K/4
2K/4/1/X

TP17

AR98

0/4/X

PEX16_PRSNT-

PEX16_PRSNT- 16

CLK_REQG_L/OSCIN/EGPIO132
USB_OC0_L/AGPIO16
USB_OC1_L/TDI/AGPIO17
USB_OC2_L/TCK/AGPIO18
USB_OC3_L/TDO/AGPIO24
AZ_BITCLK

SPKR/AGPIO91

AW 23

BLINK/AGPIO11

AT5

SPKR

SPKR

AZ_SDIN0
AZ_SDIN1

C

26

AZ_SDIN2
AZ_RST_L
AZ_SYNC
AZ_SDOUT

AN23
AP23

RTCCLK

2K/4/1/X

18

SMBCLK1
SMBDATA1

CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131

FANIN0/AGPIO84

1K/4/1

SMBCLK
SMBDATA

AK3
AK2

CLK_REQ2_L/AGPIO116

FANOUT0/AGPIO85

AR118

AU25
AV25

D

2.2K/4/1
2.2K/4/1

3VDUAL

LPC_PME_L/AGPIO22

AGPIO9/SGPIO0_DATAOUT

AZ_BIT_CLK

3VDUAL
AR80
AR81

ESPI_RESET_L/KBRST_L

AGPIO5/DEVSLP0

TP16

AW 12
AU13
AV13
AT14

SMBCLK1
SMBDATA1

TEST1/TMS

ABC23

100P/4/NPO/50V/J/X

SD INTERFACE

SYS_RESET_L/AGPIO1

SDA0/I2C2_SDA/EGPIO114

SLP_S3-

AW 11
AV12
ABC22
100P/4/NPO/50V/J/X

AN5
AM3
AM4
AL5

PWR_BTN_L/AGPIO0

SYS_RSTL
PCIE_WAKE-

EGPIO98

22/4
22/4

2.2K/4/1
2.2K/4/1

LPC_RST_L

EGPIO96

26

AR31
AR53

RTCCLK

RTCCLK

AP8

RTCCLK

A_RTC_XI

AW 5

X32K_X1

A_RTC_XO

AW 6

TEST46[13]

AL4

APU_TEST46

TP7

AZ_SDATA_IN0

8.2K/4/X

AXR1

20M/4

X32K_X2

AM4 REV 0.92
PART 4 OF 12

3

AM4/[10SC1-P01331-01R_10SC1-P01331-02R]

A_Q3

2

1

IN(H)

SEL

6

2

GND

VCC

5

3

IN(L)

OUT

4

CORETYPE1

AX1
32.768K/12.5p/20ppm/TF38/35K/D

1

5,20,23

4

3VDUAL

A_VDD18S5

B

AX1

3VDUAL
A_Q3_4

AR12

22K/4

NC7SB3157P6X_NL/SC70-6/[10TT1-123157-10R]/X
AR127

RSMRST-

AXC1
15P/4/NPO/50V/J

AXC2
15P/4/NPO/50V/J SHW/D0.64*5.08*6.74

ABC21
1u/4/X5R/6.3V/K

B

0/4

A_Q5
A_VDD18S5

AR113

0/4/X

A_Q5_1

3VDUAL

1

IN(H)

SEL

6

2

GND

VCC

5

IN(L)

OUT

4

3

CORETYPE1

5,20,23

3VDUAL
A_Q5_4

AR93

8.2K/4

RTCCLK

NC7SB3157P6X_NL/SC70-6/[10TT1-123157-10R]

Internal Debug Only
TEST0
0

TEST1
0

TEST2
0

A

Description
FCH TAP accessible from APU when TAPEN is asserted
FCH JTAG pins overloaded for multiple functions, in this
configuration the FCH JTAG are used as non-JTAG pins

ORTCXO
ORTCR1

20M/4

A

ORTCXI

0

0

1

Reserve

0

1

X

Reserve

4

RTC

1

1

TMS

0

TMS

1

FCH JTAG multi-function pins are configured as JTAG
pins, in this configuration the FCH TAP can be
accessed from FCH JTAG pins
Use on JTAG only, Yuba JTAG enable.

ORTCX
32.768K/12.5p/20ppm/TF38/35K/D

1

XI

ORTCXO

2

XO

RTC_INT-

3
4
9

VDD

8

CLKOUT

7

INT-

SCL

6

SMBCLK1

VSS
BGND

SDA

5

SMBDATA1

ORTCX
ORTC2
12p/4/NPO/50V/J

ORTC1
12p/4/NPO/50V/J

PCF85063TP/HWSON8
SHW/D0.64*5.08*6.74

8

7

6

5

4

RTCVDD3
TP12
Title

3

1

2

ORTCXI

AM4 MISC
Size
Document Number
Custom
Date:

3

Rev

GA-B350M-D2

Tuesday, November 01, 2016
2

Sheet

1.02
7
1

of

33

Vcore EDC =125A
Vcore 0.75~1.5V
VCORE

Vcore SOC EDC=75A
Vcore SOC 0.75~1.2V
VCORE_SOC

AM4L
POWER

VDDIO Max=15.5A
VDDIO_MEM AM4F

M7
N3
N6
P2

R7
T3
T6
T9
U2
U10
V9
V11
W3
W6
W 10
W 12
Y2
Y9
Y11
Y13
AA7
AA10
AA12
AB3
AB6
AB9
AB11
AB13
AC2
AC10
AC12
AD7
AD9
AD11

AD13
AE3
AE6
AE10
AE12
AF2
AF9
AF11
AF13
AG7
AG10
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AG26
AH3
AH6
AH9
AH11
AH13
AH15
AH17
AH19
AH21
AH23
AH25

AH27
AJ2
AJ10
AJ12
AJ14
AJ22
AJ24
AK7
AK9
AK11
AK13
AL3
AL6
AL10
AL12
AL14
AM2
AM8
AN7
AN10
AN13
AP3
AP9
AP12
AR2
AT4
AU3
AU6
AU9
AU12

AU15
AV5
AV8
AV11
AV14

A_VDDP
POWER

VDDIO_MEM_S3

VDDP

VDDIO_MEM_S3

VDDP

VDDIO_MEM_S3

VDDP

VDDIO_MEM_S3

VDDP

VDDIO_MEM_S3

VDDP

VDDIO_MEM_S3

VDDP

VDDIO_MEM_S3

VDDP

VDDIO_MEM_S3

VDDP

VDDIO_MEM_S3

VDDP

AM18
AM19
AM20
AN18
AN19
AN20
AP18
AP19
AP20

VDDP Max=8.5A

VDDIO_MEM_S3
VDDIO_MEM_S3

A_Q1

VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3

AM15

VDDIO_AUDIO

★ DONE

1

3VDUAL

2

A_V15S5

3

VDDIO_MEM_S3

VDDIO AUDIO 1.5/1.8V
VDDIO AUDIO Max=0.25A
Realtek suggest: 1.5V

VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3

VIN

AM4 1.5V, 250mA
5

VOUT

A_V15S5

R1

GND
EN

4

FB

A_R5
1K/4/1
A_Q1_FB

A_BC2
22P/4/NPO/50V/J
A_V15S5

A_BC1
2.2u/4/X5R/6.3V/M

Vout=0.8*(R1+R2)/R2

R2

A_R6
1.13K/4/1

VDDIO_MEM_S3
VDDIO_MEM_S3

VDD_18

VDDIO_MEM_S3

VDD_18

AJ20
AK20

A_BC6
2.2u/4/X5R/6.3V/M

A_VDD1V8
REGULATOR AP7365-WG-7 DII[10GL4-067365-01R]

VDD18 Max=2A

VDDIO_MEM_S3
VDDIO_MEM_S3

★ DONE

VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3

VDDCR_SOC_S5

VDDIO_MEM_S3
VDDIO_MEM_S3

VDD_33

VDDIO_MEM_S3

VDD_33

AJ21
AK21

For STR FAIL ISSUE

VCC3

VDD33 Max=0.25A

VDDIO_MEM_S3
VDDIO_MEM_S3

AC9
10u/6/X5R/6.3V/M

★ DONE

VDDIO_MEM_S3
VDDIO_MEM_S3

AC10
10u/6/X5R/6.3V/M

VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3

VDDP_S5

VDDIO_MEM_S3

VDDP_S5

AJ16
AJ17

A_VDDPS5

VDDP S5 Max=1A

VDDIO_MEM_S3
VDDIO_MEM_S3

3VDUAL

★ DONE

VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3

VDDCR_SOC_S5

VDDIO_MEM_S3

VDDCR_SOC_S5

AJ18
AK18

A_R3
8.2K/4/1

VDDCR_SOC_S5

VDDCR SOC S5 Max=0.9A

VDDIO_MEM_S3

A_VDD18S5

VDDIO_MEM_S3

A_C2
1u/4/X5R/6.3V/K

VDDIO_MEM_S3
VDDIO_MEM_S3

5VDUAL

VDDIO_MEM_S3
VDDIO_MEM_S3

VDD_18_S5

VDDIO_MEM_S3

VDD_18_S5

AJ15
AK15

1

A_VDD18S5
A_Q2_EN

VDDP18 S5 Max=0.5A

VDDIO_MEM_S3

A_R4
2.2/4

VDDIO_MEM_S3

★ DONE

VDDIO_MEM_S3
VDDIO_MEM_S3

A_Q2

2
3

3VDUAL

4

VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3

VDD_33_S5

VDDIO_MEM_S3

VDD_33_S5

AJ19
AK19

3VDUAL

A_C1
1u/4/X5R/6.3V/K

VDD33_S5 Max=0.25A

VDDIO_MEM_S3

POK
EN
VIN

PGND

VDDIO_MEM_S3

CNTL

HAC11
1u/4/X5R/6.3V/K

9

K36
K39
L32
L35
L38
M29
M31
M34
M37
N28
N30
N33
N36
N39
P27
P29
P32
P35
P38

R28
R31
R34
R37
T27
T29
T33
T36
T39
U28
U30
U32
U35
U38
V27
V29
V31
V34
V37
W 28
W 33
W 34
W 36
W 39
Y27
Y29
Y31
Y32
Y35
Y38

AA28
AA34
AA37
AB27
AB29
AB31
AB32
AB33
AB36
AB39
AC28
AC30
AC32
AC35
AC38
AD27
AD29
AD31
AD34
AD37
AE28
AE30
AE33
AE36
AE39
AF27
AF29
AF32
AF35
AF38

AG33
AG34
AG35
AG37
AH39

GND

8

FB

7

VOUT

6

REFIN

5

R2

AM4 1.8V, 500mA

A_R1
127K/4/1

A_C3

A_C4

A_C5
1u/4/X5R/6.3V/K

A_Q2_FB
0.1u/4/X7R/16V/K/X
22u/8/X5R/6.3V/M

A_VDD18S5

R1

RT9018B-18GSP/SO8/3A

A_R2
100K/4/1

A_VDD18S5

0.8*[(R1+R2)/R1] = Vout

SPEC. MAX :1.9W.

A_C6
2.2u/4/X5R/6.3V/M

VDDIO_MEM_S3

★ DONE

VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3
VDDIO_MEM_S3

VDDBT_RTC_G

AL15

RTCVDD

VDDBT_RTC_G Max=4.5uA

AM4 REV 0.92
PART 6 OF 12

AM4/[10SC1-P01331-01R_10SC1-P01331-02R]

20mil

AQ8
3VDUAL
18

RB

1

1K/4/1

20mil
BAT
BAT-SK/BK/P/S/D/SN

CR2032

+

BAT
CR2032

ABC11
0.1U/4/X7R/16V/K

RTCVDD3
ABC12
1U/4/X5R/6.3V/K

3

VDDCR_SOC

VDDCR_CPU